# US 11,114,537 B2 · Enhancement-mode high electron mobility transistor

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- Number: US 11,114,537 B2
- Document ID: US11114537B2
- Status: Granted
- Kind: B2
- Application number: 16/748,192
- Filed: 2020-01-21
- Published: 2020-07-23
- Granted: 2021-09-07
- Earliest claimed: 2019-01-23
- Assignees: Imec Vzw
- Applicants: Imec Vzw
- Inventors: Steve Stoffels; Niels Posthuma; Brice De Jaeger
- Web page: https://patentgrep.com/patent/US11114537B2

## CPC

- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/6738: {Schottky barrier electrodes}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/01: Manufacture or treatment
- H10D 64/0124: {to Group III-V semiconductors}
- H10D 64/64: Electrodes comprising a Schottky barrier to a semiconductor
- H10P 50/667: {by liquid etching only}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 64/411: {for FETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Example embodiments relate to enhancement-mode high electron mobility transistors. One embodiment includes a method for manufacturing an enhancement-mode high electron mobility transistor. The method includes providing a stack of layers. The stack of layers includes a substrate, a III-V channel layer over the substrate, a III-V barrier layer on the channel layer, a p-doped III-V layer on the III-V barrier layer, and a Schottky contact interlayer on the p-doped III-V layer. The p-doped III-V layer has a first surface area. The Schottky contact interlayer has a second surface area. The second surface area is less than the first surface area. The second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered. The method also includes depositing a metal gate on the Schottky contact interlayer.

## Claims

### Claim 1

A method for manufacturing an enhancement-mode high electron mobility transistor, wherein the method comprises:
providing a stack of layers comprising:
a substrate;
a III-V channel layer over the substrate;
a III-V barrier layer on the III-V channel layer;
a p-doped III-V layer on the III-V barrier layer, wherein the p-doped III-V layer has a first surface area; and
a Schottky contact interlayer on the p-doped III-V layer, wherein the Schottky contact interlayer has a surface that is in contact with the p-doped III-V layer and that has a second surface area, wherein the second surface area is less than the first surface area, and wherein the second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered by the Schottky contact interlayer; and
depositing a metal gate on the Schottky contact interlayer, thereby forming an interface between the metal gate and the Schottky contact interlayer such that entire interface has a third surface area, wherein the third surface area is less than the second surface area.

### Claim 2 (depends on 1)

The method of claim 1, wherein providing the stack of layers comprises:
providing a stack of layers comprising:
the substrate;
the III-V channel layer over the substrate;
the III-V barrier layer on the III-V channel layer;
the p-doped III-V layer on the III-V barrier layer;
the Schottky contact interlayer; and
a hard mask on the Schottky contact interlayer;
laterally wet-etching part of the Schottky contact interlayer to form:
the Schottky contact interlayer having the second surface area; and
a gap between the p-doped III-V layer and the hard mask; and
removing at least part of the hard mask to expose at least part of the Schottky contact interlayer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the III-V channel layer comprises a GaN layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the III-V barrier layer comprises an AlGaN layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the Schottky contact interlayer comprises a TiN interlayer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the Schottky contact interlayer has a thickness between 1 nm and 50 nm.

### Claim 7 (depends on 1)

The method of claim 1, wherein the metal gate comprises at least two layers differing in their chemical nature.

### Claim 8 (depends on 1)

The method of claim 1, wherein the metal gate comprises at least one layer comprising Al, Cu, or an alloy of Al and Cu.

### Claim 9 (depends on 8)

The method of claim 8, wherein the metal gate comprises:
a first TiN layer on the Schottky contact interlayer;
a first Ti layer on the first TiN layer;
an alloy of Cu and Al on the first Ti layer;
a second Ti layer on the alloy of Cu and Al; and
a second TiN layer on the second Ti layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein the first TiN layer has a thickness between 10 nm and 80 nm.

### Claim 11 (depends on 10)

The method of claim 10, wherein a combined thickness of the Schottky contact interlayer and the first TiN layer is between from 11 nm to 81 nm.

### Claim 12 (depends on 1)

The method of claim 1, further comprising:
depositing a dielectric layer on the Schottky contact interlayer;
opening part of the dielectric layer to form an opening exposing at least part of the Schottky contact interlayer; and
depositing the metal gate on the Schottky contact interlayer in the opening.

### Claim 13 (depends on 12)

The method of claim 12, wherein depositing the dielectric layer on the Schottky contact interlayer comprises:
depositing an aluminum oxide layer on the Schottky contact interlayer; and
depositing a silicon oxide layer on the aluminum oxide layer.

### Claim 14 (depends on 1)

The method of claim 1, wherein the metal gate comprises a material different from a material forming the Schottky contact interlayer.

### Claim 15

An enhancement-mode high electron mobility transistor comprising:
a stack of layers comprising:
a substrate:
a III-V channel layer over the substrate;
a III-V barrier layer on the III-V channel layer;
a p-doped III-V layer on the III-V barrier layer, wherein the p-doped III-V layer has a first surface area;
a Schottky contact interlayer on the p-doped III-V layer, wherein the Schottky contact interlayer has a surface that is in contact with the p-doped III-V layer and that has a second surface area, wherein the second surface area is less than the first surface area, and wherein the second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered by the Schottky contact interlayer; and
a metal gate on the Schottky contact interlayer, wherein an interface exists between the metal gate and the Schottky contact interlayer such that the entire interface has a third surface area, wherein the third surface area is less than the second surface area.

### Claim 16 (depends on 15)

The enhancement-mode high electron mobility transistor of claim 15, wherein the III-V channel layer comprises a GaN layer.

### Claim 17 (depends on 15)

The enhancement-mode high electron mobility transistor of claim 15, wherein the III-V barrier layer comprises an AlGaN layer.

### Claim 18 (depends on 15)

The enhancement-mode high electron mobility transistor of claim 15, wherein the Schottky contact interlayer comprises a TiN interlayer.

### Claim 19 (depends on 15)

The enhancement-mode high electron mobility transistor of claim 15, wherein the Schottky contact interlayer has a thickness between 1 nm and 50 nm.

### Claim 20 (depends on 15)

The enhancement-mode high electron mobility transistor of claim 15, wherein the metal gate comprises at least two layers differing in their chemical nature.