# US 11,114,536 B1 · Semiconductor device having multiple dimensions of gate structures and method for fabricating the same

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- Number: US 11,114,536 B1
- Document ID: US11114536B1
- Status: Granted
- Kind: B1
- Application number: 16/801,685
- Filed: 2020-02-26
- Published: 2021-08-26
- Granted: 2021-09-07
- Earliest claimed: 2020-02-26
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Cheng-Ling Yang
- Web page: https://patentgrep.com/patent/US11114536B1

## CPC

- H10D 64/514: {characterised by the insulating layers}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/01: Manufacture or treatment
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 64/666: {the conductor further comprising additional layers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including an array area and a peripheral area adjacent to the array area, a first gate structure positioned in the array area, and a second gate structure positioned in the peripheral area. A width of the first gate structure is less than a width of the second gate structure, and a depth of the first gate structure is less than a depth of the second gate structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate comprising an array area and a peripheral area adjacent to the array area;
a first gate structure positioned in the array area; and
a second gate structure positioned in the peripheral area;
wherein a width of the first gate structure is less than a width of the second gate structure, and a depth of the first gate structure is less than a depth of the second gate structure;
wherein the first gate structure comprises a first gate insulating layer inwardly positioned in the array area, a first gate conductive layer positioned on the first gate insulating layer, and a first bottom capping layer positioned on the first gate conductive layer, wherein a top surface of the first bottom capping layer is at a same vertical level as a top surface of the substrate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a top surface of the first gate conductive layer is at a vertical level higher than a vertical level of top surfaces of the first gate insulating layer.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising a plurality of first doped regions positioned adjacent to two sides of the first gate structure, wherein bottom surfaces of the first doped regions are at a same vertical level as the top surface of the first gate conductive layer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, further comprising a first gate liner positioned between the first gate insulating layer and the first gate conductive layer.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein top surfaces of the first gate liner are at a vertical level lower than the vertical level of the top surface of the first gate conductive layer.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, further comprising a second gate structure comprising a second gate insulating layer inwardly positioned in the peripheral area, a second gate conductive layer positioned on the second gate insulating layer, and a second bottom capping layer positioned on the second gate conductive layer, wherein a top surface of the second bottom capping layer is at a same vertical level as the top surface of the substrate, and a top surface of the second gate conductive layer is at a vertical level lower than the vertical level of the top surface of the first gate conductive layer.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, further comprising a plurality of second doped regions positioned adjacent to two sides of the second gate structure, wherein bottom surfaces of the second doped regions are at a same vertical level as the top surface of the second gate conductive layer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, further comprising a first top capping layer positioned on the first bottom capping layer.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising a plurality of third doped regions positioned adjacent to two sides of the first top capping layer and on the plurality of first doped regions.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further comprising a plurality of first isolation structures positioned in the array area and a plurality of second isolation structures positioned in the peripheral area, wherein the first gate structure is positioned between an adjacent pair of the plurality of first isolation structures and the second gate structure is positioned between an adjacent pair of the plurality of second isolation structures.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein a depth of the plurality of second isolation structures is greater than a depth of the plurality of first isolation structures.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein a porosity of the first top capping layer is between about 10% and about 30%.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the first gate insulating layer has a thickness between about 13 angstroms and about 20 angstroms.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein the first gate liner has a thickness between about 10 angstroms and about 15 angstroms.

### Claim 15

A method for fabricating a semiconductor device, comprising:
providing a substrate comprising an array area and a peripheral area adjacent to the array area;
forming a first gate structure in the array area; and
forming a second gate structure in the peripheral area and having a width greater than a width of the first gate structure and a depth greater than a depth of the first gate structure;
wherein the first gate structure comprises a first gate insulating layer inwardly positioned in the array area, a first gate conductive layer positioned on the first gate insulating layer, and a first bottom capping layer positioned on the first gate conductive layer, wherein a top surface of the first bottom capping layer is at a same vertical level as a top surface of the substrate.

### Claim 16 (depends on 15)

The method for fabricating the semiconductor device of claim 15, wherein the first gate structure and the second gate structure are concurrently formed.

### Claim 17 (depends on 16)

The method for fabricating the semiconductor device of claim 16, further comprising:
forming a plurality of first doped regions adjacent to two sides of the first gate structure and in the array area; and
forming a plurality of second doped regions adjacent to two sides of the second gate structure and in the peripheral area.

### Claim 18 (depends on 17)

The method for fabricating the semiconductor device of claim 17, further comprising:
forming a plurality of third doped regions on the plurality of first doped regions; and
forming a plurality of fourth doped regions on the plurality of second doped regions.

### Claim 19 (depends on 18)

The method for fabricating the semiconductor device of claim 18, wherein the plurality of first doped regions and the plurality of third doped regions have different electrical types.