# US 11,114,531 B2 · Semiconductor device, method for manufacturing semiconductor device, inverter circuit, driving device, vehicle, and elevator

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- Number: US 11,114,531 B2
- Document ID: US11114531B2
- Status: Granted
- Kind: B2
- Application number: 15/891,984
- Filed: 2018-02-08
- Published: 2018-10-25
- Granted: 2021-09-07
- Earliest claimed: 2017-04-24
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Tatsuo Shimizu; Masayasu Miyata; Hirotaka Nishino; Yoshihiko Moriyama; Yuichiro Mitani
- Web page: https://patentgrep.com/patent/US11114531B2

## CPC

- H10D 62/8325: {Silicon carbide}
- H10D 12/031: {of IGBTs}
- H10D 12/035: {Etching a recess in the emitter region (having a recessed gate H10D12/038)}
- H10D 12/441: {Vertical IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/154: {Dispositions}
- H10D 62/158: {Dispositions}
- H10D 64/0115: {to silicon carbide}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 30/2042: {into crystalline silicon carbide}
- H10P 30/21: {of electrically active species}
- H10P 30/218: {characterised by the implantation in a compound semiconductor of both electrically active and inactive species in the same semiconductor region to be doped n-type or p-type}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device according to an embodiment includes a first electrode; a second electrode; a gate electrode; an n-type first silicon carbide region positioned between the first electrode and the second electrode and between the gate electrode and the second electrode; a p-type second silicon carbide region positioned between the first electrode and the first silicon carbide region; a third silicon carbide region of metal containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt), positioned between the first electrode and the second silicon carbide region and spaced apart from the first silicon carbide region; and a gate insulating layer positioned between the gate electrode and the second silicon carbide region.

## Claims

### Claim 1

A semiconductor device comprising:
a first electrode;
a second electrode;
a gate electrode;
an n-type first silicon carbide region positioned between the first electrode and the second electrode and between the gate electrode and the second electrode;
a p-type second silicon carbide region positioned between the first electrode and the first silicon carbide region;
a third silicon carbide region positioned between the first electrode and the p-type second silicon carbide region and spaced apart from the n-type first silicon carbide region, the third silicon carbide region being metallized silicon carbide containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt), and the third silicon carbide region having a crystal structure of silicon carbide; and
a gate insulating layer positioned between the gate electrode and the p-type second silicon carbide region, wherein
the at least one element is present at the carbon site of the crystal structure of silicon carbide, and
a concentration of the at least one element in the third silicon carbide region is 1×1019 cm−3 to 5×1022 cm−3.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the third silicon carbide region contains silicon (Si) present at a carbon site of a crystal structure of silicon carbide.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein a thickness of the third silicon carbide region in a direction toward the second electrode from the first electrode is 0.01 μm to 0.5 μm.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein a sheet resistance of the third silicon carbide region is 0.5Ω/□ or less.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein a work function of the third silicon carbide region is 3.7 eV or less.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, further comprising a p-type fourth silicon carbide region positioned between the p-type second silicon carbide region and the first electrode and having a higher p-type impurity concentration than that of the p-type second silicon carbide region.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, further comprising an n-type fifth silicon carbide region between the p-type second silicon carbide region and the third silicon carbide region.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, further comprising a sixth silicon carbide region of metal containing the at least one element, the p-type second silicon carbide region interposed between the third silicon carbide region and the sixth silicon carbide region, and the sixth silicon carbide region being in contact with the gate insulating layer and the n-type first silicon carbide region.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, further comprising an n-type seventh silicon carbide region positioned between the n-type first silicon carbide region and the second electrode and having a higher n-type impurity concentration than that of the n-type first silicon carbide region.

### Claim 10 (depends on 1)

An inverter circuit comprising the semiconductor device according to claim 1.

### Claim 11 (depends on 1)

A driving device comprising the semiconductor device according to claim 1.

### Claim 12 (depends on 1)

A vehicle comprising the semiconductor device according to claim 1.

### Claim 13 (depends on 1)

An elevator comprising the semiconductor device according to claim 1.