# US 11,114,530 B2 · Quantum well stacks for quantum dot devices

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- Number: US 11,114,530 B2
- Document ID: US11114530B2
- Status: Granted
- Kind: B2
- Application number: 16/648,442
- Filed: 2017-12-17
- Published: 2021-02-04
- Granted: 2021-09-07
- Earliest claimed: 2017-12-17
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Nicole K. Thomas; James S. Clarke; Jessica M. Torres; Ravi Pillarisetty; Kanwaljit Singh; Payam Amin; Hubert C. George; Jeanette M. Roberts; Roman Caudillo; David J. Michalak; Zachary R. Yoscovits; Lester Lampert
- Web page: https://patentgrep.com/patent/US11114530B2

## CPC

- H10D 62/812: {Single quantum well structures}
- H10D 30/402: {Single electron transistors; Coulomb blockade transistors}
- H10D 48/383: {Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects}
- H10D 48/3835: {Semiconductor qubit devices comprising a plurality of quantum mechanically interacting semiconductor quantum dots, e.g. Loss-DiVincenzo spin qubits}
- H10D 48/385: {Devices using spin-polarised carriers}
- H10D 48/40: Devices controlled by magnetic fields
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/01: Manufacture or treatment
- H10D 64/27: Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/473: {having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/80: characterised by the materials
- H10D 62/84: being selenium or tellurium only
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.

## Claims

### Claim 1

A quantum dot device, comprising:
a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; and
a gate above the quantum well stack,
wherein the isotopically purified material includes silicon and germanium.

### Claim 2 (depends on 1)

The quantum dot device of claim 1, wherein the silicon includes 29Si in an amount less than 4 atomic-percent.

### Claim 3 (depends on 1)

The quantum dot device of claim 1, wherein the germanium includes 73Ge in an amount less than 7 atomic-percent.

### Claim 4 (depends on 1)

The quantum dot device of claim 1, wherein the isotopically purified material is a first isotopically purified material, the quantum well stack further includes a buffer layer, the buffer layer includes a second isotopically purified material, the gate includes a gate dielectric, and the quantum well layer is between the buffer layer and the gate dielectric.

### Claim 5 (depends on 4)

The quantum dot device of claim 4, wherein the second isotopically purified material includes zinc, cadmium, tellurium, selenium, sulfur, iron, lead, tin, or carbon.

### Claim 6 (depends on 4)

The quantum dot device of claim 4, wherein a thickness of the buffer layer is greater than 25 nanometers.

### Claim 7 (depends on 4)

The quantum dot device of claim 4, wherein the quantum well stack further includes a barrier layer, the barrier layer includes a third isotopically purified material, and the barrier layer is between the quantum well layer and the gate dielectric.

### Claim 8 (depends on 4)

The quantum dot device of claim 4, further comprising:
a barrier layer, wherein the buffer layer is between the quantum well layer and the barrier layer.

### Claim 9 (depends on 1)

The quantum dot device of claim 1, wherein the gate includes a gate dielectric, the isotopically purified material is a first isotopically purified material, and the gate dielectric includes a second isotopically purified material.

### Claim 10 (depends on 9)

The quantum dot device of claim 9, wherein the second isotopically purified material includes silicon.

### Claim 11 (depends on 9)

The quantum dot device of claim 9, wherein the second isotopically purified material includes hafnium.

### Claim 12 (depends on 11)

The quantum dot device of claim 11, wherein the hafnium of the second isotopically purified material includes 177Hf in an amount less than 18 atomic-percent.

### Claim 13 (depends on 9)

The quantum dot device of claim 9, wherein the second isotopically purified material includes zirconium, titanium, strontium, or yttrium.

### Claim 14 (depends on 9)

The quantum dot device of claim 9, wherein the gate dielectric is on the quantum well layer.

### Claim 15 (depends on 1)

The quantum dot device according to claim 1, wherein:
the quantum dot device is a quantum computing device that includes a quantum processing device and a non-quantum processing device,
the quantum processing device includes the quantum well stack and the gate, and
the non-quantum processing device is coupled to the quantum processing device and configured to control a voltage applied to the gate.

### Claim 16

A quantum computing device, comprising:
a quantum processing device, wherein the quantum processing device includes a quantum well stack including a quantum well layer and a buffer layer, the quantum well layer includes first isotopically purified material, the buffer layer includes a second isotopically purified material, and the quantum processing device further includes at least one gate above the quantum well stack to control quantum dot formation in the quantum well stack; and
a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the at least one gate,
wherein:
the gate at least one gate includes a gate dielectric,
the quantum well layer is between the buffer layer and the gate dielectric,
the quantum computing device further includes a barrier layer, and
the buffer layer is between the quantum well layer and the barrier layer.

### Claim 17 (depends on 16)

The quantum computing device of claim 16, further comprising:
a memory device to store data generated by quantum dots formed in the quantum well stack during operation of the quantum processing device.

### Claim 18

A quantum dot device, comprising:
a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; and
a gate above the quantum well stack;
wherein the isotopically purified material includes at least one of zinc, cadmium, tellurium, selenium, sulfur, iron, lead, tin, and carbon.

### Claim 19 (depends on 18)

The quantum dot device according to claim 18, wherein:
the gate includes a gate dielectric and a gate metal,
the gate dielectric above the quantum well stack, and
the gate dielectric is between the quantum well layer and the gate metal.

### Claim 20 (depends on 18)

The quantum dot device according to claim 18, wherein:
the quantum dot device is a quantum computing device that includes a quantum processing device and a non-quantum processing device,
the quantum processing device includes the quantum well stack and the gate, and
the non-quantum processing device is coupled to the quantum processing device and configured to control a voltage applied to the gate.