# US 11,114,527 B2 · Semiconductor device and method for manufacturing same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,114,527 B2 - Document ID: US11114527B2 - Status: Granted - Kind: B2 - Application number: 16/815,636 - Filed: 2020-03-11 - Published: 2020-07-02 - Granted: 2021-09-07 - Earliest claimed: 2019-02-14 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Makoto Koshimizu; Hideki Niwayama; Kazuyuki Umezu; Hiroki Soeda; Atsushi Tachigami; Takeshi Iijima - Web page: https://patentgrep.com/patent/US11114527B2 ## CPC - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]} - H10D 30/0285: {using formation of insulating sidewall spacers} - H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]} - H10D 30/65: Lateral DMOS [LDMOS] FETs - H10D 62/104: {having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats} - H10D 64/516: {the thicknesses being non-uniform} - H10D 84/0179: {the gate conductors having different shapes or dimensions} - H10D 84/0181: {Manufacturing their gate insulating layers} - H10D 84/0188: {Manufacturing their isolation regions} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS} - H10W 10/0121: {in regions recessed from the surface, e.g. in trenches or grooves} - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10D 30/0212: {using self-aligned silicidation} - H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers} - H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 62/153: {Impurity concentrations or distributions} - H10D 62/157: {Impurity concentrations or distributions} - H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current} - H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge - H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D 64/62: Electrodes ohmically coupled to a semiconductor - H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other. ## Claims ### Claim 1 A semiconductor device comprising: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate and including an active region, the active region including: a source region; and a drain region formed away from the source region with a channel length; a first device isolation portion formed in the semiconductor layer, the first device isolation portion surrounding the active region of the semiconductor layer in a plan view; a first terrace insulating film formed between the source region and the drain region, the first terrace insulating film being formed on the semiconductor layer; a gate insulating film formed on the semiconductor layer; a gate electrode formed on the gate insulating film, the gate electrode being partially formed on the first terrace insulating film; a first buried layer of a second conductivity type different from a first conductivity type of the semiconductor substrate, the first buried layer formed in the semiconductor layer; and a second buried layer of the first conductivity type formed on the first buried layer; and a junction isolating part of the first conductivity type surrounding the first device isolation portion in the plan view, the junction isolating part reaching the second buried layer, wherein a thickness of the first terrace insulating film is smaller than a thickness of the first device isolation portion, wherein a cell pitch which is a distance between a center part of the source region and a center part of the drain region is shorter than 5 μm in a channel length direction, wherein, in the plan view, the source region, the drain region, the first device isolation portion, the gate electrode and the junction isolating part overlap with the first buried layer, and wherein, in the plan view, the source region, the drain region, the first device isolation portion, and the gate electrode overlap with the second buried region. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, comprising: a second device isolation portion surrounding the junction isolating part in the plan view; and a well of the second conductivity type surrounding the second device isolation portion in the plan view, the well reaching the first buried layer. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the thickness of the first terrace insulating film is 70 nm or more and 200 nm or less. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the thickness of the first terrace insulating film is 70 nm or more and 200 nm or less. ### Claim 5 (depends on 3) The semiconductor device according to claim 3, wherein the thickness of the first terrace insulating film is 70 nm or more and 100 nm or less. ### Claim 6 (depends on 4) The semiconductor device according to claim 4, wherein the thickness of the first terrace insulating film is 70 nm or more and 100 nm or less. ### Claim 7 (depends on 3) The semiconductor device according to claim 3, wherein a planar shape of the first terrace insulating film is a rectangle. ### Claim 8 (depends on 4) The semiconductor device according to claim 4, wherein a planar shape of the first terrace insulating film is a rectangle. ### Claim 9 (depends on 3) The semiconductor device according to claim 3, wherein a planar shape of the first terrace insulating film is an octagon. ### Claim 10 (depends on 4) The semiconductor device according to claim 4, wherein a planar shape of the first terrace insulating film is an octagon. ### Claim 11 (depends on 3) The semiconductor device according to claim 3, comprising an interlayer insulating film formed on the semiconductor layer so as to cover the gate electrode; a first plug formed in the interlayer insulating film and formed on a first portion of the source region; and a second plug formed in the interlayer insulating film and formed on a second portion of the source region, wherein the active region includes a back-gate region surrounded by the source region in the plan view, wherein a silicide film is formed on an upper surface of each of the back-gate region and the source region, and wherein the first plug and the second plug are electrically connected to the back-gate region and the source region through the silicide film. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, wherein the first plug overlaps with the first portion of the source region and a third portion of the back-gate region in the plan view, and wherein the second plug overlaps with the second portion of the source region and a fourth portion of the back-gate region in the plan view. ### Claim 13 (depends on 11) The semiconductor device according to claim 11, wherein the back-gate region is located between the first portion of the source region and the second portion of the source region in the channel length direction. ### Claim 14 (depends on 12) The semiconductor device according to claim 12, wherein the back-gate region is located between the first portion of the source region and the second portion of the source region in the channel length direction. ### Claim 15 (depends on 1) The semiconductor device according to claim 1, wherein the cell pitch which is substantially 3.1 μm in the channel length direction. ### Claim 16 (depends on 1) The semiconductor device according to claim 1, comprising: a first semiconductor region configuring an emitter, the first semiconductor region having a second conductivity type different from a first conductivity type of the semiconductor substrate; a second semiconductor region configuring a base, the second semiconductor region surrounding the first semiconductor region, the second semiconductor region having the first conductivity type; a third semiconductor region configuring a collector, the third semiconductor region formed away from the second semiconductor region, a second terrace insulating film formed between the second semiconductor region and the third second semiconductor region, the second terrace insulating film formed on the semiconductor layer; and a second device isolation portion formed in the semiconductor layer, the second device isolation portion surrounding the third semiconductor region in the plan view, wherein a thickness of the second terrace insulating film is smaller than a thickness of the second device isolation portion. ### Claim 17 A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer formed on the semiconductor substrate and including an active region, the active region including: a back-gate region; a source region surrounding the back-gate region in a plan view; and a drain region surrounding the source region in the plan view, a first device isolation portion formed in the semiconductor layer, the first device isolation portion surrounding the active region of the semiconductor layer in the plan view; a first terrace insulating film formed between the source region and the drain region, the first terrace insulating film formed on the semiconductor layer; a gate insulating film formed on the semiconductor layer; a gate electrode formed on the gate insulating film, the gate electrode being partially formed on the first terrace insulating film; an interlayer insulating film formed on the semiconductor layer so as to cover the gate electrode; a first plug formed in the interlayer insulating film and formed on a first portion of the source region; a second plug formed in the interlayer insulating film and formed on a second portion of the source region; a first buried layer of a second conductivity type different from a first conductivity type of the semiconductor substrate, the first buried layer being formed in the semiconductor layer; a second buried layer of the first conductivity type formed on the first buried layer; and a junction isolating part of the first conductivity type surrounding the first device isolation portion in the plan view, the junction isolating part reaching the second buried layer, wherein a thickness of the first terrace insulating film is smaller than a thickness of the first device isolation portion, wherein a cell pitch which is a distance between a center part of the source region and a center part of the drain region is shorter than 5 μm in a channel length direction, wherein, in the plan view, the back-gate region, the source region, the drain region, the first device isolation portion, the gate electrode and the junction isolating part overlap with the first buried layer, and wherein, in the plan view, the back-gate region, the source region, the drain region, the first device isolation portion, and the gate electrode overlap with the second buried region. ### Claim 18 (depends on 17) The semiconductor device according to claim 17, comprising: a second device isolation portion surrounding the junction isolating part in the plan view; and a well of the second conductivity type surrounding the second device isolation portion in the plan view, the well reaching the first buried layer. ### Claim 19 (depends on 17) The semiconductor device according to claim 17, wherein the thickness of the first terrace insulating film is 70 nm or more and 200 nm or less. ### Claim 20 (depends on 19) The semiconductor device according to claim 19, wherein the thickness of the first terrace insulating film is 70 nm or more and 100 nm or less. ### Claim 21 (depends on 19) The semiconductor device according to claim 19, wherein a planar shape of the first terrace insulating film is a rectangle. ### Claim 22 (depends on 19) The semiconductor device according to claim 19, wherein a planar shape of the first terrace insulating film is an octagon. ### Claim 23 (depends on 17) The semiconductor device according to claim 17, comprising a silicide film formed on an upper surface of each of the back-gate region and the source region, wherein the first plug and the second plug are electrically connected to the back-gate region and the source region through the silicide film. ### Claim 24 (depends on 17) The semiconductor device according to claim 17, wherein the first plug overlaps with the first portion of the source region and a third portion of the back-gate region in the plan view, and wherein the second plug overlaps with the second portion of the source region and a fourth portion of the back-gate region in the plan view. ### Claim 25 (depends on 17) The semiconductor device according to claim 17, wherein the back-gate region is located between the first portion of the source region and the second portion of the source region in the channel length direction. ### Claim 26 (depends on 17) The semiconductor device according to claim 17, wherein the cell pitch is substantially 3.1 μm in the channel length direction. ### Claim 27 (depends on 17) The semiconductor device according to claim 17, comprising: a first semiconductor region configuring an emitter, the first semiconductor region having a second conductivity type different from a first conductivity type of the semiconductor substrate; a second semiconductor region configuring a base, the second semiconductor region surrounding the first semiconductor region, the second semiconductor region having the first conductivity type; a third semiconductor region configuring a collector, the third semiconductor region formed away from the second semiconductor region, a second terrace insulating film formed between the second semiconductor region and the third second semiconductor region, the second terrace insulating film formed on the semiconductor layer; and a second device isolation portion formed in the semiconductor layer, the second device isolation portion surrounding the third semiconductor region in the plan view, wherein a thickness of the second terrace insulating film is smaller than a thickness of the second device isolation portion.