# US 11,114,478 B2 · Thin film transistor and manufacture method thereof, array substrate and manufacture method thereof

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- Number: US 11,114,478 B2
- Document ID: US11114478B2
- Status: Granted
- Kind: B2
- Application number: 16/561,315
- Filed: 2019-09-05
- Published: 2020-05-07
- Granted: 2021-09-07
- Earliest claimed: 2018-11-01
- Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd.
- Applicants: Hefei Xinsheng Optoelectronics Technology Co., Ltd.; BOE Technology Group Co., Ltd.
- Inventors: Leilei Cheng
- Web page: https://patentgrep.com/patent/US11114478B2

## CPC

- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/443: {adapted for preventing breakage, peeling or short circuiting}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6723: {having light shields}
- H10D 30/6729: {characterised by the electrodes}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 50/73: {using masks for insulating materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A thin film transistor and a manufacture method thereof, an array substrate and a manufacture method thereof are provided. The manufacture method of the thin film transistor includes: providing a base substrate; and forming a gate electrode, a first electrode, a second electrode and a semiconductor layer of the thin film transistor on the base substrate. At least one of the gate electrode, the first electrode and the second electrode includes N portions that are stacked in a direction perpendicular to the base substrate, adjacent two of the N portions are in direct contact with each other, and N is a positive integer more than or equal to 2. The method includes: performing N patterning processes to respectively form the N portions.

## Claims

### Claim 1

A manufacture method of a thin film transistor, comprising:
providing a base substrate; and
forming a gate electrode, a first electrode, a second electrode, and a semiconductor layer of the thin film transistor on the base substrate, wherein at least one of a group consisting of the gate electrode, the first electrode, and the second electrode comprises N portions that are stacked in a direction perpendicular to the base substrate, adjacent two portions of the N portions are in direct contact with each other, and N is a positive integer more than or equal to 2,
wherein the method comprises: performing N patterning processes to respectively form the N portions;
wherein the gate electrode comprises N1 portions that are stacked in the direction perpendicular to the base substrate, the first electrode comprises N2 portions that are stacked in the direction perpendicular to the base substrate, and the second electrode comprises N3 portions that are stacked in the direction perpendicular to the base substrate; N1, N2, and N3 are all positive integers more than or equal to 2;
in a direction from a position close to the base substrate to a position away from the base substrate, the N1 portions are sequentially a first portion, a second portion . . . , and a N1-th portion, the N2 portions are sequentially a first portion, a second portion . . . , and a N2-th portion, and the N3 portions are sequentially a first portion, a second portion . . . , and a N3-th portion; and
a M1-th portion of the gate electrode, a M2-th portion of the first electrode, and a M3-th portion of the second electrode are simultaneously formed by one patterning process using a same mask, wherein M1 is a positive integer less than or equal to N1, M2 is a positive integer less than or equal to N2, and M3 is a positive integer less than or equal to N3.

### Claim 2 (depends on 1)

The manufacture method of the thin film transistor according to claim 1, wherein N1=N2=N3 and M1=M2=M3.

### Claim 3 (depends on 1)

A manufacture method of an array substrate, comprising: forming the thin film transistor by the manufacture method of the thin film transistor according to claim 1.

### Claim 4 (depends on 3)

The manufacture method of the array substrate according to claim 3, further comprising:
forming a signal line on the base substrate, wherein the signal line comprises N4 portions that are stacked in the direction perpendicular to the base substrate, adjacent two portions of the N4 portions are in direct contact with each other, and N4 is a positive integer more than or equal to 2,
wherein the forming the signal line comprises: performing N4 patterning processes to respectively form the N4 portions.

### Claim 5 (depends on 4)

The manufacture method of the array substrate according to claim 4, wherein a total thickness of the signal line in the direction perpendicular to the base substrate is more than 5500 angstroms, and a thickness in the direction perpendicular to the base substrate of each portion of the N4 portions is not more than 5500 angstroms.

### Claim 6 (depends on 4)

The manufacture method of the array substrate according to claim 4, wherein the array substrate comprises a plurality of the signal lines extending in a same direction, and an interval between adjacent signal lines of the plurality of the signal lines is less than or equal to 6 μm.

### Claim 7 (depends on 4)

The manufacture method of the array substrate according to claim 4, wherein a same mask is used to perform the N4 patterning processes.

### Claim 8 (depends on 4)

The manufacture method of the array substrate according to claim 4, wherein
in a direction from a position close to the base substrate to a position away from the base substrate, the N4 portions of the signal line are sequentially a first portion, a second portion . . . , and a N4-th portion,
a M4-th portion of the signal line, a M1-th portion of the gate electrode, a M2-th portion of the first electrode, and a M3-th portion of the second electrode are simultaneously formed by one patterning process using a same mask, and M1 is a positive integer less than or equal to N1, M2 is a positive integer less than or equal to N2, M3 is a positive integer less than or equal to N3, and M4 is a positive integer less than or equal to N4.

### Claim 9 (depends on 4)

The manufacture method of the array substrate according to claim 4, wherein the signal line comprises at least one of a group consisting of a gate line electrically connected to the gate electrode, a data line electrically connected to the second electrode, a common voltage line providing a common voltage, and a ground line.

### Claim 10 (depends on 9)

The manufacture method of the array substrate according to claim 9, wherein the data line intersects with and is insulated from the gate line and the manufacture method comprises:
forming the gate line, the gate electrode, the first electrode and the second electrode simultaneously by a same patterning process;
forming an interlayer insulating layer covering the gate line, the gate electrode, the first electrode and the second electrode, wherein the interlayer insulating layer comprises a via hole exposing the second electrode; and
forming the data line on the interlayer insulating layer, and the data line is electrically connected to the second electrode through the via hole.

### Claim 11 (depends on 9)

The manufacture method of the array substrate according to claim 9, further comprising: forming a light shielding layer, wherein the light shielding layer is on a side, which is away from the gate electrode, of the semiconductor layer, and an orthographic projection of the light shielding layer on the base substrate at least partially overlaps an orthographic projection of a channel region of the semiconductor layer of the thin film transistor on the base substrate, wherein
the common voltage line or the ground line is electrically connected to the light shielding layer.

### Claim 12 (depends on 1)

The manufacture method of the thin film transistor according to claim 1, wherein a total thickness of the N portions in the direction perpendicular to the base substrate is more than 5500 angstroms, and a thickness in the direction perpendicular to the base substrate of each portion of the N portions is not more than 5500 angstroms.

### Claim 13 (depends on 1)

The manufacture method of the thin film transistor according to claim 1, wherein a same mask is used to perform the N patterning processes.

### Claim 14

A manufacture method of a thin film transistor, comprising:
providing a base substrate; and
forming a gate electrode, a first electrode, a second electrode, and a semiconductor layer of the thin film transistor on the base substrate, wherein at least one of a group consisting of the gate electrode, the first electrode, and the second electrode comprises N portions that are stacked in a direction perpendicular to the base substrate, adjacent two portions of the N portions are in direct contact with each other, and N is a positive integer more than or equal to 2,
wherein the method comprises: performing N patterning processes to respectively form the N portions,
wherein the semiconductor layer comprises an upper surface away from the base substrate, a first side surface and a second side surface that intersect the upper surface, and the first side surface is opposite to the second side surface, and
the first electrode is in direct contact with the upper surface and the first side surface, and the second electrode is in direct contact with the upper surface and the second side surface.

### Claim 15 (depends on 14)

The manufacture method of the thin film transistor according to claim 14, further comprising: forming a gate insulating layer, wherein the gate insulating layer comprises:
a first portion between the gate electrode and the semiconductor layer so as to insulate the gate electrode and the semiconductor layer, wherein the first portion exposes the upper surface, contacting with the first electrode and the second electrode, of the semiconductor layer, exposes the first side surface, contacting with the first electrode, of the semiconductor layer, and exposes the second side surface, contacting with the second electrode, of the semiconductor layer;
a second portion between the first electrode and the base substrate; and
a third portion between the second electrode and the base substrate.

### Claim 16 (depends on 15)

The manufacture method of the thin film transistor according to claim 15, wherein the forming the gate insulating layer comprises:
forming a gate insulating material film;
forming a photoresist layer covering the gate insulating material film;
exposing and developing the photoresist layer using a two-tone mask to obtain a photoresist remaining region, a photoresist partially remaining region, and a photoresist removing region, wherein the photoresist remaining region is a region where the first portion of the gate insulating layer is to be formed, the photoresist partially remaining region is a region where the second portion and the third portion of the gate insulating layer are to be formed, and the photoresist removing region is a region except the photoresist remaining region and the photoresist partially remaining region;
performing a first etching process to remove a portion of the gate insulating material film in the photoresist removing region;
performing an ashing process to remove a portion of the photoresist layer in the photoresist partially remaining region and thin a portion of the photoresist layer in the photoresist remaining region;
performing a second etching process to thin a portion of the gate insulating material film in the photoresist partially remaining region, so as to form the first portion, the second portion, and the third portion of the gate insulating layer; and
removing a portion of the photoresist layer in the photoresist remaining region.

### Claim 17

A thin film transistor, comprising: a gate electrode, a first electrode, a second electrode, and a semiconductor layer, wherein the gate electrode comprises N1 portions that are stacked in a direction perpendicular to a base substrate, the first electrode comprises N2 portions that are stacked in the direction perpendicular to the base substrate, and the second electrode comprises N3 portions that are stacked in the direction perpendicular to the base substrate; N1, N2, and N3 are all positive integers more than or equal to 2;
adjacent two portions of the N1 portions are in direct contact with each other, adjacent two portions of the N2 portions are in direct contact with each other, and adjacent two portions of the N3 portions are in direct contact with each other;
in a direction from a position close to the base substrate to a position away from the base substrate, the N1 portions are sequentially a first portion, a second portion . . . , and a N1-th portion, the N2 portions are sequentially a first portion, a second portion . . . , and a N2-th portion, and the N3 portions are sequentially a first portion, a second portion . . . , and a N3-th portion; and
a M1-th portion of the gate electrode, a M2-th portion of the first electrode, and a M3-th portion of the second electrode are in a same layer, wherein M1 is a positive integer less than or equal to N1, M2 is a positive integer less than or equal to N2, and M3 is a positive integer less than or equal to N3.

### Claim 18 (depends on 17)

The thin film transistor according to claim 17, wherein the semiconductor layer comprises an upper surface, a first side surface and a second side surface that intersect the upper surface, and the first side surface is opposite to the second side surface,
the first electrode is in direct contact with the upper surface and the first side surface, and the second electrode is in direct contact with the upper surface and the second side surface.

### Claim 19 (depends on 18)

The thin film transistor according to claim 18, wherein the thin film transistor is on the base substrate and further comprises a gate insulating layer, and the gate insulating layer comprises:
a first portion between the gate electrode and the semiconductor layer so as to insulate the gate electrode and the semiconductor layer, wherein the first portion exposes the upper surface, contacting with the first electrode and the second electrode, of the semiconductor layer, exposes the first side surface, contacting with the first electrode, of the semiconductor layer, and exposes the second side surface, contacting with the second electrode, of the semiconductor layer;
a second portion between the first electrode and the base substrate; and
a third portion between the second electrode and the base substrate.