# US 11,114,477 B2 · Array substrate and manufacturing method thereof

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- Number: US 11,114,477 B2
- Document ID: US11114477B2
- Status: Granted
- Kind: B2
- Application number: 16/094,315
- Filed: 2018-08-23
- Published: 2021-07-29
- Granted: 2021-09-07
- Earliest claimed: 2018-07-04
- Assignees: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Applicants: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Inventors: Caiqin Chen; Xing Ming
- Web page: https://patentgrep.com/patent/US11114477B2

## CPC

- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 86/0223: {comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/411: {characterised by materials, geometry or structure of the substrates}
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 59/1201: {Manufacture or treatment}
- H10K 59/1213: {the pixel elements being TFTs}
- H10K 59/122: Pixel-defining structures or layers, e.g. banks
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- H10K 77/111: {Flexible substrates}
- H10K 2102/311: {Flexible OLED}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

In a method for manufacturing an array substrate, a first photoresist pattern is formed on a buffer layer of a non-display region and the buffer layer uncovered by the first photoresist pattern is removed to form a first via hole in the non-display region. A second via hole is formed on the basis of the first via hole. The second via hole is connected to the first via hole. By forming the first via hole in the non-display region and forming the second via hole on the basis of the first via hole, completeness of film layers is ensured and product yield is improved.

## Claims

### Claim 1

A method for manufacturing an array substrate, comprising:
forming a buffer layer on a substrate, the substrate comprising a display region and a non-display region;
forming a first photoresist pattern on the buffer layer of the non-display region and removing a part of the buffer layer to form a first via hole in the non-display region;
forming an insulating layer on the buffer layer of the non-display region and the first via hole; and
forming a second photoresist pattern on the insulating layer of the non-display region and removing a part of the insulating layer to form a second via hole in the non-display region, the second photoresist pattern corresponding to the first via hole and the second via hole connected to the first via hole,
wherein the insulating layer at least partially covers the first via hole and a cross-sectional area of the second via hole is less than or equal to a cross-sectional area of the first via hole, and
wherein a thickness of the first via hole is between 0.7 micrometer and 0.9 micrometer and a thickness of the second via hole is between 0.6 micrometer and 0.8 micrometer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein after the step of removing the part of the insulating layer to form the second via hole in the non-display region, the method further comprises:
filling an organic material into the first via hole and the second via hole to form an organic insulating layer in the first via hole and the second via hole, wherein the organic insulating layer contacts the substrate via the first via hole and the second via hole; and
sequentially forming a metal layer, an organic flat layer, and a pixel defining layer on the organic insulating layer.

### Claim 3 (depends on 2)

The method according to claim 2, wherein the step of forming the first photoresist pattern on the buffer layer of the non-display region and removing the part of the buffer layer to form the first via hole in the non-display region comprises:
forming a first photoresist layer on the buffer layer of the non-display region and processing the first photoresist layer by exposure and development to form the first photoresist pattern on the buffer layer of the non-display region; and
etching the buffer layer uncovered by the first photoresist pattern to form the first via hole in the non-display region.

### Claim 4 (depends on 2)

The method according to claim 2, wherein the step of forming the second photoresist pattern on the insulating layer of the non-display region and removing the part of the insulating layer to form the second via hole in the non-display region comprises:
forming a second photoresist layer on the insulating layer of the non-display region and processing the second photoresist layer by exposure and development to form the second photoresist pattern on the insulating layer of the non-display region; and
etching the insulating layer uncovered by the second photoresist pattern to form the second via hole in the non-display region.

### Claim 5 (depends on 4)

The method according to claim 4, further comprising:
sequentially forming a thin-film transistor pattern and the insulating layer on the buffer layer of the display region;
forming the second photoresist layer on the insulating layer and processing the second photoresist layer by the exposure and the development to form a third photoresist pattern and a fourth photoresist pattern on the insulating layer of the display region; and
removing the insulating layer uncovered by the third photoresist pattern and the fourth photoresist pattern to form a third via hole and a fourth via hole in the display region,
wherein the third via hole and the fourth via hole run through the thin-film transistor pattern and the insulating layer and are disposed at two sides of the thin-film transistor pattern,
wherein a source electrode is formed in the third via hole, a drain electrode is formed in the fourth via hole, and the source electrode and the drain electrode at least covers a part of the insulating layer, and
wherein an organic flat layer, an anode, a pixel defining layer, and a spacer are sequentially formed on the source electrode and the drain electrode.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the insulating layer is made of polyimide resin or poly(methyl methacrylate).

### Claim 7 (depends on 1)

The method according to claim 1, wherein a flexible material is filled into the first via hole and the second via hole to increase flexibility of the array substrate.

### Claim 8

A method for manufacturing an array substrate, comprising:
forming a buffer layer on a substrate, the substrate comprising a display region and a non-display region;
forming a first photoresist pattern on the buffer layer of the non-display region and removing a part of the buffer layer to form a first via hole in the non-display region;
forming an insulating layer on the buffer layer of the non-display region and the first via hole; and
forming a second photoresist pattern on the insulating layer of the non-display region and removing a part of the insulating layer to form a second via hole in the non-display region, wherein the second photoresist pattern corresponds to the first via hole and the second via hole is connected to the first via hole.

### Claim 9 (depends on 8)

The method according to claim 8, wherein after the step of removing the part of the insulating layer to form the second via hole in the non-display region, the method further comprises:
filling an organic material into the first via hole and the second via hole to form an organic insulating layer in the first via hole and the second via hole, wherein the organic insulating layer contacts the substrate via the first via hole and the second via hole; and
sequentially forming a metal layer, an organic flat layer, and a pixel defining layer on the organic insulating layer.

### Claim 10 (depends on 9)

The method according to claim 9, wherein the step of forming the first photoresist pattern on the buffer layer of the non-display region and removing the part of the buffer layer to form the first via hole in the non-display region comprises:
forming a first photoresist layer on the buffer layer of the non-display region and processing the first photoresist layer by exposure and development to form the first photoresist pattern on the buffer layer of the non-display region; and
etching the buffer layer uncovered by the first photoresist pattern to form the first via hole in the non-display region.

### Claim 11 (depends on 9)

The method according to claim 9, wherein the step of forming the second photoresist pattern on the insulating layer of the non-display region and removing the part of the insulating layer to form the second via hole in the non-display region comprises:
forming a second photoresist layer on the insulating layer of the non-display region and processing the second photoresist layer by exposure and development to form the second photoresist pattern on the insulating layer of the non-display region; and
etching the insulating layer uncovered by the second photoresist pattern to form the second via hole in the non-display region.

### Claim 12 (depends on 11)

The method according to claim 11, further comprising:
sequentially forming a thin-film transistor pattern and the insulating layer on the buffer layer of the display region;
forming the second photoresist layer on the insulating layer and processing the second photoresist layer by the exposure and the development to form a third photoresist pattern and a fourth photoresist pattern on the insulating layer of the display region; and
removing the insulating layer uncovered by the third photoresist pattern and the fourth photoresist pattern to form a third via hole and a fourth via hole in the display region,
wherein the third via hole and the fourth via hole run through the thin-film transistor pattern and the insulating layer and are disposed at two sides of the thin-film transistor pattern,
wherein a source electrode is formed in the third via hole, a drain electrode is formed in the fourth via hole, and the source electrode and the drain electrode at least covers a part of the insulating layer, and
wherein an organic flat layer, an anode, a pixel defining layer, and a spacer are sequentially formed on the source electrode and the drain electrode.