# US 11,114,476 B2 · Manufacturing method of TFT array substrate, TFT array substrate and display panel

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- Number: US 11,114,476 B2
- Document ID: US11114476B2
- Status: Granted
- Kind: B2
- Application number: 16/076,186
- Filed: 2018-06-11
- Published: 2021-04-01
- Granted: 2021-09-07
- Earliest claimed: 2018-04-13
- Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Inventors: Chuanbao Luo; Jiangbo Yao
- Web page: https://patentgrep.com/patent/US11114476B2

## CPC

- H10D 86/0231: {using masks, e.g. half-tone masks}
- G02F 1/136222: {Colour filters incorporated in the active matrix substrate}
- G02F 1/136231: {for reducing the number of lithographic steps}
- G02F 1/13625: {Patterning using multi-mask exposure}
- G02F 1/136295: {Materials; Compositions; Manufacture processes}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6732: {Bottom-gate only TFTs}
- H10D 30/6746: {Amorphous silicon}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- G02F 2202/103: a-Si
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

A manufacturing method of a TFT array substrate is provided, comprising: depositing and forming a gate and a gate scanning line; depositing sequentially a gate insulating layer, an active layer and a second metal layer; depositing and forming a first photoresist layer and a second photoresist layer on the second metal layer; first photoresist layer comprising a first-stage photoresist layer, second-stage photoresist layer and third-stage photoresist layer with increasing thickness, the first-stage photoresist layer being in the middle of the first photoresist layer and a channel being formed; ashing to remove first-stage photoresist layer, forming a source and a drain by etching; and ashing to remove the second-stage photoresist layer, and then depositing a passivation layer as a whole; stripping third-stage photoresist layer and second photoresist layer, depositing and forming a pixel electrode and a common electrode.

## Claims

### Claim 1

A manufacturing method of a TFT array substrate comprises:
providing a rigid substrate, depositing a first metal layer on the rigid substrate, and patterning the first metal layer to form a gate electrode and a gate scanning line;
depositing sequentially a gate insulating layer, an active layer and a second metal layer on the gate and the gate scanning line;
coating photoresist on the second metal layer and patterning the photoresist to form a first photoresist layer and a second photoresist layer; wherein the first photoresist layer comprises a first-stage photoresist layer, a second-stage photoresist layer and a third-stage photoresist layer; the thickness of the second-stage photoresist layer is larger than that of the first-stage photoresist layer, and the thickness of the third-stage photoresist layer is larger than that of the second-stage photoresist layer;
the first-stage photoresist layer is disposed in the middle of the first photoresist layer and a channel is formed; and the thickness of the second photoresist layer is larger than that of the second-stage photoresist layer;
etching a region of the second metal layer, a region of the active layer and a region of the gate insulating layer, which are outside the channel and uncovered by the first photoresist layer and the second photoresist layer to expose the rigid substrate;
performing ashing treatment on the first photoresist layer and the second photoresist layer to remove the first-stage photoresist layer, and forming a source electrode, and a drain electrode by etching;
performing ashing treatment on the second-stage photoresist layer, the third-stage photoresist layer and the second photoresist layer to remove the second-stage photoresist layer, and then depositing a passivation layer as a whole;
stripping the third-stage photoresist layer and the second photoresist layer, and depositing a transparent conductive layer and patterning the transparent conductive layer to form a pixel electrode and a common electrode.

### Claim 2 (depends on 1)

The manufacturing method as claimed in claim 1, wherein the active layer comprises a first amorphous silicon film and a second amorphous silicon film sequentially stacked on the gate insulating layer, and the first amorphous silicon film is disposed between the gate insulating layer and the second amorphous silicon film.

### Claim 3 (depends on 2)

The manufacturing method as claimed in claim 2, wherein the material of the first amorphous silicon film comprises amorphous silicon and the material of the second amorphous silicon film comprises impurity ion-doped amorphous silicon.

### Claim 4 (depends on 2)

The manufacturing method as claimed in claim 2, wherein the process of forming the source electrode and the drain electrode by etching comprises: etching the second metal layer after ashing the first-stage photoresist layer; the method further comprises etching the second amorphous silicon film to form source, drain, and conductive channel regions.

### Claim 5 (depends on 1)

The manufacturing method as claimed in claim 1, wherein a data line layer is formed from the second metal layer covered by the second photoresist layer after etching the region of the second metal layer, the region of the active layer and the region of the gate insulating layer, which are outside the channel and uncovered by the first photoresist layer and the second photoresist layer.

### Claim 6 (depends on 5)

The manufacturing method as claimed in claim 5, wherein the gate scanning line and the data line layer are bridged through the common electrode.

### Claim 7 (depends on 1)

The manufacturing method as claimed in claim 1, wherein the material of the transparent conductive layer comprises at least one of indium tin oxide, indium oxide zinc, aluminum zinc oxide and indium gallium zinc oxide.

### Claim 8 (depends on 1)

The manufacturing method as claimed in claim 1, wherein the material of the passivation layer comprises at least one of silicon oxide and silicon nitride.

### Claim 9 (depends on 1)

The manufacturing method as claimed in claim 1, wherein the material of the first metal layer comprises at least one of copper, aluminum, neodymium, chromium, molybdenum, titanium and silver.

### Claim 10 (depends on 1)

The manufacturing method as claimed in claim 1, wherein the material of the second metal layer comprises at least one of copper, aluminum, neodymium, chromium, molybdenum, titanium and silver.

### Claim 11 (depends on 1)

A TFT array substrate prepared by the manufacturing method as claimed in claim 1.

### Claim 12 (depends on 11)

The TFT array substrate as claimed in claim 11, wherein the active layer comprises a first amorphous silicon film and a second amorphous silicon film sequentially stacked on the gate insulating layer, and the first amorphous silicon film is disposed between the gate insulating layer and the second amorphous silicon film.

### Claim 13 (depends on 12)

The TFT array substrate as claimed in claim 12, wherein the material of the first amorphous silicon film comprises amorphous silicon and the material of the second amorphous silicon film comprises impurity ion-doped amorphous silicon.

### Claim 14 (depends on 12)

The TFT array substrate as claimed in claim 12, wherein the process of forming the source electrode and the drain electrode by etching comprises: etching the second metal layer after ashing the first-stage photoresist layer; the method further comprises etching the second amorphous silicon film to form source, drain, and conductive channel regions.

### Claim 15 (depends on 11)

The TFT array substrate as claimed in claim 11, wherein a data line layer is formed from the second metal layer covered by the second photoresist layer after etching the region of the second metal layer, the region of the active layer and the region of the gate insulating layer, which are outside the channel and uncovered by the first photoresist layer and the second photoresist layer.

### Claim 16 (depends on 15)

The TFT array substrate as claimed in claim 15, wherein the gate scanning line and the data line layer are bridged through the common electrode.

### Claim 17 (depends on 11)

The TFT array substrate as claimed in claim 11, wherein the material of the transparent conductive layer comprises at least one of indium tin oxide, indium oxide zinc, aluminum zinc oxide and indium gallium zinc oxide.

### Claim 18 (depends on 11)

The TFT array substrate as claimed in claim 11, wherein the material of the passivation layer comprises at least one of silicon oxide and silicon nitride.

### Claim 19 (depends on 1)

A display panel, wherein the display panel comprises a TFT array substrate prepared by the manufacturing method as claimed in claim 1.