# US 11,114,471 B2 · Thin film transistors having relatively increased width and shared bitlines

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- Number: US 11,114,471 B2
- Document ID: US11114471B2
- Status: Granted
- Kind: B2
- Application number: 16/633,559
- Filed: 2017-09-26
- Published: 2020-07-02
- Granted: 2021-09-07
- Earliest claimed: 2017-09-26
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Brian S. Doyle; Abhishek A. Sharma; Ravi Pillarisetty; Prashant Majhi; Elijah V. Karpov
- Web page: https://patentgrep.com/patent/US11114471B2

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 30/026: {having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow (of LDMOS H10D30/0289)}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 76/204: {of organic photoresist masks}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Thin film transistors having relatively increased width and shared bitlines are described. In an example, an integrated circuit structure includes a plurality of transistors formed in an insulator structure above a substrate. The plurality of transistors arranged in a column such that the respective lateral arrangement of the source, the gate, and the drain of each of the transistors aligns with an adjacent thin film transistor, wherein the plurality transistors extend vertically through the insulator structure at least two interconnect levels to provide increased relative width. A first conductive contact is formed between one of sources and drains of at least two of the plurality of transistors in the column, and the conductive contact extends through the insulator structure at least two interconnect levels.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a plurality of transistors formed in an insulator structure above a substrate, each comprising a lateral arrangement of:
a gate in the insulating structure, a source laterally adjacent to a first side of the gate, and a drain laterally adjacent to an opposite a second side of the gate, the plurality of transistors arranged in a column such that the respective lateral arrangement of the source, the gate, and the drain of each of the transistors aligns with an adjacent thin film transistor, wherein the plurality transistors extend vertically through the insulator structure at least two interconnect levels to provide increased relative width; and a first conductive contact formed between one of sources and drains of at least two of the plurality of transistors in the column, and the conductive contact extends through the insulator structure at least two interconnect levels.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein the first conductive contact is formed between the drains of one or more pairs of the transistors in the column.

### Claim 3 (depends on 2)

The integrated circuit structure of claim 2, wherein the first conductive contact is formed between the drains of all the transistors in the column.

### Claim 4 (depends on 2)

The integrated circuit structure of claim 2, wherein the first conductive contact comprises a bitline.

### Claim 5 (depends on 1)

The integrated circuit structure of claim 1, wherein the first conductive contact is formed between sources of the at least two of the plurality of transistors in the column.

### Claim 6 (depends on 5)

The integrated circuit structure of claim 5, wherein the first conductive contact is formed between the sources of all of the plurality of transistors in the column.

### Claim 7 (depends on 1)

The integrated circuit structure of claim 1, wherein the first conductive contact is formed between the drains of the transistors and a second contact is formed between the sources of the transistors in the column.

### Claim 8 (depends on 1)

The integrated circuit structure of claim 1, further comprising an array of transistors in which laterally adjacent transistors in each row of the array share a common drain.

### Claim 9 (depends on 8)

The integrated circuit structure of claim 8, wherein common drains along a same column of the array are connected together by the first conductive contact, providing a shared bitline.

### Claim 10 (depends on 8)

The integrated circuit structure of claim 8, wherein the shared bitline extends a full width of the transistors.

### Claim 11 (depends on 8)

The integrated circuit structure of claim 8, wherein the shared bitline is formed by a backbone trench in the insulating structure filled with a metal material.

### Claim 12 (depends on 8)

The integrated circuit structure of claim 8, wherein the backbone trench is made laterally wider to decrease bitline resistance.

### Claim 13 (depends on 1)

The integrated circuit structure of claim 1, further comprising a semiconducting oxide material on the insulator structure, the semiconducting oxide material conformal with the topography of the insulator structure.

### Claim 14 (depends on 13)

The integrated circuit structure of claim 13, further comprising a gate electrode over a first portion of the semiconducting oxide material on the insulator structure.

### Claim 15

An integrated circuit structure, comprising:
an array of transistors formed in an insulator structure above a substrate, wherein each of the transistors comprises a lateral arrangement of:
a gate in the insulating structure, a source laterally adjacent to a first side of the gate, and a drain laterally adjacent to an opposite a second side of the gate, the array of transistors arranged in rows of laterally adjacent transistors, and columns such that the respective lateral arrangement of the source, the gate, and the drain of each of the transistors aligns with an adjacent thin film transistor in a same column, wherein the plurality transistors extend vertically through the insulator structure at least two interconnect levels to provide increased relative width; and
first conductive contacts that connect the drains along respective columns of the array such that each of the single conductive contacts are shared between neighboring pairs of transistors in each row of the array, and wherein the first conductive contact extends through the insulator structure at least two interconnect levels.

### Claim 16 (depends on 15)

The integrated circuit structure of claim 15, wherein the first conductive contacts comprise shared bitlines.

### Claim 17 (depends on 16)

The integrated circuit structure of claim 16, wherein the shared bitlines extend into the insulator structure a full width of the transistors.

### Claim 18 (depends on 15)

The integrated circuit structure of claim 15, wherein the shared bitlines are formed by a backbone trench in the insulating structure filled with a metal material.

### Claim 19 (depends on 15)

The integrated circuit structure of claim 15, wherein the backbone trench is made laterally wider to decrease bitline resistance.

### Claim 20 (depends on 15)

The integrated circuit structure of claim 15, further comprising second conductive contacts formed between sources of the at least two transistors in each of the columns.

### Claim 21 (depends on 20)

The integrated circuit structure of claim 20, wherein the second conductive contacts are formed between the sources of all of the plurality of transistors in the column.

### Claim 22 (depends on 15)

The integrated circuit structure of claim 15, further comprising a semiconducting oxide material on the insulator structure, the semiconducting oxide material conformal with the topography of the insulator structure.

### Claim 23 (depends on 22)

The integrated circuit structure of claim 22, further comprising a gate electrode over a first portion of the semiconducting oxide material on the insulator structure.

### Claim 24

A method of fabricating an array of thin film transistors, the method comprising:
forming an insulating structure over a substrate to a desired interconnect level over conductive lines representing source and drain lines on a substrate;
forming vias and backbone trenches in the insulating structure;
filling the vias and backbone trenches with conductive metal to form conductive contacts representing source lines and drain lines, wherein the conductive contacts formed in the backbone trenches span columns of the array to form shared bitlines;
forming a photoresist mask on top of the insulating structure with openings defining locations of channel areas between the source and drain lines;
forming channel area trenches by etching the insulating structure in the locations defining the channel areas to a same interconnect level as the insulating;
forming a semiconducting oxide material in the channel trench areas;
forming a gate dielectric layer over the semiconducting oxide material in the channel area trenches;
forming a gate electrode on the gate dielectric layer to fill-in the channel trench areas forming vias on the gate electrode; and
forming wordlines on an uppermost surface of the vias, wherein the wordlines are laid out perpendicular to the shared bitlines.

### Claim 25 (depends on 24)

The method of claim 24, further comprising forming vias and backbone trenches to a same interconnect level as the insulating structure.