# US 11,114,468 B2 · Thin film transistor array substrate

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- Number: US 11,114,468 B2
- Document ID: US11114468B2
- Status: Granted
- Kind: B2
- Application number: 16/475,137
- Filed: 2019-03-25
- Published: 2020-08-06
- Granted: 2021-09-07
- Earliest claimed: 2018-12-29
- Applicants: Wuhan China Star Optoelectronics Technology Co., Ltd.
- Inventors: Xin Zhang; Lisheng Li; Peng He
- Web page: https://patentgrep.com/patent/US11114468B2

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 86/60: wherein the TFTs are in active matrices
- B82Y 40/00: Manufacture or treatment of nanostructures
- G02F 1/1362: Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)}
- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

A thin film transistor (TFT) array substrate is provided. The TFT array substrate includes a display device plate and a semiconductor layer disposed on the display device plate. A thickness of the semiconductor layer is less than or equal to 35 nm.

## Claims

### Claim 1

A thin film transistor (TFT) array substrate, comprising:
a display device plate; and
a semiconductor layer disposed on the display device plate, wherein a thickness of the semiconductor layer is less than or equal to 35 nm, and the semiconductor layer is generally “n” shaped;
wherein the semiconductor layer comprises an active island and semiconductor lines connected to the active island and perpendicularly disposed to the active island, a width of the active island is less than or equal to 1.8 μm; and
wherein the semiconductor lines comprise ion lightly doped areas and channel connecting areas, and a width of the ion lightly doped area is less than the width of the active island.

### Claim 2 (depends on 1)

The TFT array substrate according to claim 1, wherein a width of the channel connecting area is equal to the width of the active island.

### Claim 3 (depends on 1)

The TFT array substrate according to claim 1, wherein a width of the channel connecting area is less than the width of the active island.

### Claim 4 (depends on 3)

The TFT array substrate according to claim 3, wherein the width of the ion lightly doped area is equal to the width of the channel connecting area.

### Claim 5 (depends on 3)

The TFT array substrate according to claim 3, wherein the width of the ion lightly doped area is less than the width of the channel connecting area.

### Claim 6 (depends on 1)

The TFT array substrate according to claim 1, wherein the display device plate comprises:
a base substrate;
a buffer layer disposed on the base substrate;
a gate insulated layer disposed on the buffer layer;
a gate metallic layer disposed on the gate insulated layer;
an interlayer dielectric disposed on the gate insulated layer and covering the gate metallic layer; and
a source/drain metallic layer disposed on the interlayer dielectric, wherein the semiconductor layer is disposed on the buffer layer and covered by the gate insulated layer, the semiconductor lines further comprise bonding areas, and the source/drain metallic layer is connected to the bonding areas.

### Claim 7 (depends on 6)

The TFT array substrate according to claim 6, wherein a width of the bonding area is greater than the width of the active island.

### Claim 8 (depends on 6)

The TFT array substrate according to claim 6, wherein a width of the gate metallic layer is greater than a length of the channel connecting area.

### Claim 9

A TFT array substrate, comprising:
a display device plate; and
a semiconductor layer disposed on the display device plate, wherein a thickness of the semiconductor layer is less than or equal to 35 nm;
wherein the semiconductor layer comprises an active island and semiconductor lines connected to the active island and perpendicularly disposed to the active island, a width of the active island is less than or equal to 1.8 μm; and
wherein the semiconductor lines comprise ion lightly doped areas and channel connecting areas, and a width of the ion lightly doped area is less than the width of the active island.

### Claim 10 (depends on 9)

The TFT array substrate according to claim 9, wherein a width of the channel connecting area is equal to the width of the active island.

### Claim 11 (depends on 9)

The TFT array substrate according to claim 9, wherein a width of the channel connecting area is less than the width of the active island.

### Claim 12 (depends on 11)

The TFT array substrate according to claim 11, wherein the width of the ion lightly doped area is equal to the width of the channel connecting area.

### Claim 13 (depends on 11)

The TFT array substrate according to claim 11, wherein the width of the ion lightly doped area is less than the width of the channel connecting area.

### Claim 14 (depends on 9)

The TFT array substrate according to claim 9, wherein the display device plate comprises:
a base substrate;
a buffer layer disposed on the base substrate;
a gate insulated layer disposed on the buffer layer;
a gate metallic layer disposed on the gate insulated layer;
an interlayer dielectric disposed on the gate insulated layer and covering the gate metallic layer; and
a source/drain metallic layer disposed on the interlayer dielectric, wherein the semiconductor layer is disposed on the buffer layer and covered by the gate insulated layer, the semiconductor lines further comprise bonding areas, and the source/drain metallic layer is connected to the bonding areas.

### Claim 15 (depends on 14)

The TFT array substrate according to claim 14, wherein a width of the bonding area is greater than the width of the active island.

### Claim 16 (depends on 14)

The TFT array substrate according to claim 14, wherein a width of the gate metallic layer is greater than a length of the channel connecting area.