# US 11,114,466 B2 · IC products formed on a substrate having localized regions of high resistivity and methods of making such IC products > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,114,466 B2 - Document ID: US11114466B2 - Status: Granted - Kind: B2 - Application number: 16/774,087 - Filed: 2020-01-28 - Published: 2021-07-29 - Granted: 2021-09-07 - Earliest claimed: 2020-01-28 - Assignees: GlobalFoundries U.S. Inc. - Applicants: GLOBALFOUNDRIES U.S. Inc. - Inventors: Sipeng Gu; Jiehui Shu; Haiting Wang - Web page: https://patentgrep.com/patent/US11114466B2 ## CPC - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10P 36/07: {of silicon-on-insulator structures} - H10D 86/01: Manufacture or treatment - H10P 90/1906: {Preparing SOI wafers} - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers} - H10P 30/204: {into Group IV semiconductors} - H10P 30/208: {of electrically inactive species} - H10P 50/642: {Chemical etching} - H10P 90/1922: {using silicon etch back techniques, e.g. BESOI or ELTRAN} - H10W 10/00: Isolation regions in semiconductor bodies between components of integrated devices - H10W 10/01: {Manufacture or treatment} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract One illustrative IC product disclosed herein includes an (SOI) substrate comprising a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer. In this particular example, the IC product also includes a first region of localized high resistivity formed in the base semiconductor layer, wherein the first region of localized high resistivity has an electrical resistivity that is greater than an electrical resistivity of the material of the base semiconductor layer. The IC product also includes a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer. ## Claims ### Claim 1 An integrated circuit (IC) product, comprising: a semiconductor-on-insulator (SOI) substrate comprising a base semiconductor layer, a buried insulation layer positioned above the base semiconductor layer and an active semiconductor layer positioned above the buried insulation layer; a first region of localized high resistivity formed in the base semiconductor layer, the first region of localized high resistivity having an electrical resistivity that is greater than an electrical resistivity of a material of the base semiconductor layer; and a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer. ### Claim 2 (depends on 1) The IC product of claim 1, wherein the first region of localized high resistivity comprises an insulating material positioned within an opening in the base semiconductor layer. ### Claim 3 (depends on 2) The IC product of claim 2, wherein the opening in the base semiconductor layer extends from a back surface of the base semiconductor layer to an interface between the base semiconductor layer and the buried insulation layer. ### Claim 4 (depends on 2) The IC product of claim 2, wherein the insulating material comprises one of silicon dioxide, silicon nitride, a high-k material (a material having a k value of about 7.0 or greater), HfOx, Al2O3, Ta2O3, TiO2, BASrTiO3, BzF2, CaF2 or SrF2, the base semiconductor layer comprises silicon, the buried insulation layer comprises silicon dioxide and the active semiconductor layer comprises silicon. ### Claim 5 (depends on 1) The IC product of claim 1, wherein the material of the base semiconductor layer has a crystalline lattice structure and wherein the first region of localized high resistivity comprises a damaged region of the base semiconductor layer adjacent an interface between the base semiconductor layer with a damaged lattice structure that is different than the crystalline lattice structure. ### Claim 6 (depends on 5) The IC product of claim 5, further comprising an opening in the base semiconductor layer, wherein the opening extends from a back surface of the base semiconductor layer to the damaged region of the base semiconductor layer and wherein the opening is filled with insulating material. ### Claim 7 (depends on 1) The IC product of claim 1, wherein the first region comprising integrated circuits comprises RF integrated circuits. ### Claim 8 (depends on 1) The IC product of claim 1, wherein, when viewed in a cross-section taken through the first region of localized high resistivity and a first plane that is substantially parallel to an upper surface of the active semiconductor layer, the first region of localized high resistivity has one of a substantially circular, a substantially rectangular, a substantially square or an irregular configuration. ### Claim 9 (depends on 1) The IC product of claim 1, wherein, in a first plane that is substantially parallel to an upper surface of the active semiconductor layer, the first region of localized high resistivity has a first area and, in a second plane that is substantially parallel to the upper surface of the active semiconductor layer, the first region comprising integrated circuits has a second area, wherein the first area is greater than the second area. ### Claim 10 (depends on 1) The IC product of claim 1, wherein, in a first plane substantially parallel to an upper surface of the active semiconductor layer, the first region of localized high resistivity has a first area and, in a second plane that is substantially parallel to the upper surface of the active semiconductor layer, the first region comprising integrated circuits has a second area, wherein the first area is substantially the same as the second area. ### Claim 11 (depends on 1) The IC product of claim 1, wherein the electrical resistivity of the first region of localized high resistivity is at least about 10E3 times greater than the electrical resistivity of the material of the base semiconductor layer. ### Claim 12 (depends on 1) The IC product of claim 1, further comprising: a second region of localized high resistivity formed in the base semiconductor layer, the second region of localized high resistivity having an electrical resistivity that is greater than an electrical resistivity of the material of the base semiconductor layer, the second region of localized high resistivity being spaced apart from the first region of localized high resistivity; and a second region comprising integrated circuits formed above the active semiconductor layer, wherein the second region comprising integrated circuits is positioned vertically above the second region of localized high resistivity in the base semiconductor layer. ### Claim 13 An integrated circuit (IC) product, comprising: a semiconductor-on-insulator (SOI) substrate comprising a base semiconductor layer, a buried insulation layer positioned on the base semiconductor layer and an active semiconductor layer positioned on the buried insulation layer; a first region of localized high resistivity formed in the base semiconductor layer, the first region of localized high resistivity having an electrical resistivity that is greater than an electrical resistivity of a material of the base semiconductor layer, wherein the first region of localized high resistivity comprises an insulating material positioned within an opening in the base semiconductor layer; and a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer and wherein, in a first plane substantially parallel to an upper surface of the active semiconductor layer, the first region of localized high resistivity has a first area and, in a second plane that is substantially parallel to the upper surface of the active semiconductor layer, the first region comprising integrated circuits has a second area, wherein the first area is substantially equal to or greater than the second area. ### Claim 14 (depends on 13) The IC product of claim 13, wherein the first region comprising integrated circuits comprises RF integrated circuits. ### Claim 15 (depends on 13) The IC product of claim 13, wherein the electrical resistivity of the first region of localized high resistivity is at least about 10E3 times greater than the electrical resistivity of the material of the base semiconductor layer. ### Claim 16 (depends on 13) The IC product of claim 13, wherein the opening in the base semiconductor layer extends from a back surface of the base semiconductor layer to an interface between the base semiconductor layer and the buried insulation layer. ### Claim 17 An integrated circuit (IC) product, comprising: a semiconductor-on-insulator (SOI) substrate comprising a base semiconductor layer, a buried insulation layer positioned on the base semiconductor layer and an active semiconductor layer positioned on the buried insulation layer, the base semiconductor layer comprising a material having a layer having a crystalline lattice structure and an electrical resistivity; a first region of localized high resistivity formed in the base semiconductor layer, the first region of localized high resistivity having an electrical resistivity that is greater than the electrical resistivity of the material of the base semiconductor layer, wherein the first region of localized high resistivity comprises a damaged region of the base semiconductor layer adjacent an interface between the base semiconductor layer, the damaged region having a damaged lattice structure that is different than the crystalline lattice structure; and a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer and wherein, in a first plane substantially parallel to an upper surface of the active semiconductor layer, the first region of localized high resistivity has a first area and, in a second plane that is substantially parallel to the upper surface of the active semiconductor layer, the first region comprising integrated circuits has a second area, wherein the first area is substantially equal to or greater than the second area. ### Claim 18 (depends on 17) The IC product of claim 17, further comprising an opening in the base semiconductor layer, wherein the opening extends from a back surface of the base semiconductor layer to the damaged region of the base semiconductor layer, wherein the opening is filled with insulating material. ### Claim 19 (depends on 17) The IC product of claim 17, wherein the first region comprising integrated circuits comprises RF integrated circuits. ### Claim 20 (depends on 17) The IC product of claim 17, wherein the electrical resistivity of the first region of localized high resistivity is at least about 10E3 times greater than the electrical resistivity of the material of the base semiconductor layer.