US 11,114,465 B1 · Memory device, semiconductor device and associated method

Abstract

A memory device, including: memory cells, first conductive lines, second conductive lines, third conductive lines and fourth conductive lines. The memory cells are arranged in an array. Each memory cell includes a transistor and a capacitor connected to a gate terminal of the transistor in series. The first conductive lines extend in a first direction. Each first conductive line connects to gate terminals of transistors arranged in same column in the array. The second conductive lines extend in the first direction. Each second conductive line connects to source terminals of transistors arranged in same column in the array. The third conductive lines extend in the first direction. Each third conductive line connects to drain terminals of transistors arranged in same column in the array. The fourth conductive lines extend in a second direction. Each fourth conductive line couples to the capacitor arranged in same row in the array.

Claims20

Dependent claims

A memory device, comprising:

a plurality of memory cells arranged in an array, wherein each memory cell includes a transistor and a capacitor connected to a gate terminal of the transistor in series;
a plurality of first conductive lines, extending in a first direction, wherein each first conductive line connects to gate terminals of transistors arranged in same column in the array;
a plurality of second conductive lines, extending in the first direction, wherein each second conductive line connects to source terminals of transistors arranged in same column in the array;
a plurality of third conductive lines, extending in the first direction, wherein each third conductive line connects to drain terminals of transistors arranged in same column in the array;
and
a plurality of fourth conductive line, extending in a second direction, wherein each fourth conductive line couples to the capacitor arranged in same row in the array.

3 more elements

A method of manufacturing a semiconductor device, comprising:

providing a substrate;
forming a plurality of gate strips on the substrate, and the plurality of gate strip extend in a first direction;
forming a plurality of ferroelectric material strips above the plurality of gate strips, and the plurality of ferroelectric material strips extend in a second direction orthogonal with the first direction, wherein intersections of the gate strips and the ferroelectric material strips define an array of ferroelectric field effect transistor (FeFET);
forming a plurality of first conductive lines extending in the first direction, wherein each first conducive line connects to one of the plurality of gate strips;
forming a plurality of second conductive lines extending in the second direction, wherein each second conductive line connects to one of the plurality of ferroelectric material strips;
forming a plurality of active regions configured to be source/drain regions of FeFETs;
forming a plurality of third conductive lines extending in the first direction, wherein each third conductive line connects to source regions of FeFETs arranged in same column;
and
forming a plurality of fourth conductive lines extending in the first direction, wherein each fourth conductive line connects to drain regions of FeFETs arranged in same column.

6 more elements

Dependencies are inferred from the claim text.

Memory device, semiconductor device and associated method

Life of this patent

Memory device, semiconductor device and associated method

Life of this patent

Abstract

Claims20