# US 11,114,463 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,114,463 B2 - Document ID: US11114463B2 - Status: Granted - Kind: B2 - Application number: 16/892,384 - Filed: 2020-06-04 - Published: 2020-09-24 - Granted: 2021-09-07 - Earliest claimed: 2017-07-18 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Seung Jun Shin; Hyun Mog Park; Joong Shik Shin - Web page: https://patentgrep.com/patent/US11114463B2 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/40: characterised by the peripheral circuit region - H10B 43/10: characterised by the top-view layout - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/40: characterised by the peripheral circuit region - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)} - H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) - H10D 30/689: {Vertical floating-gate IGFETs} - H10D 30/693: {Vertical IGFETs having charge trapping gate insulators} - H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode} - H10P 50/00: Etching of wafers, substrates or parts of devices - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 20/081: {by forming openings in the dielectric parts} - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate having a first region and a second region; gate electrodes stacked perpendicularly to an upper surface of the substrate in the first region, the gate electrodes extending to different lengths in a first direction in the second region, and each of the gate electrodes including: subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other; channels extending through the gate electrodes perpendicularly to the upper surface of the substrate in the first region; and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including: first dummy channels arranged in the second region in rows and columns, the rows extending in the first direction, and the columns extending in the second direction, second dummy channels arranged in the second region on both sides of at least a portion of the gate connection portions in the second direction, the second dummy channels being arranged between two columns of the first dummy channels that are adjacent to each other along the first direction, and third dummy channels arranged in the first region adjacent to the second region. ### Claim 2 (depends on 1) The semiconductor device as claimed in claim 1, further comprising a lower isolation region passing only through some of the gate electrodes, the lower isolation region passing through at least a lowermost gate electrode of the gate electrodes in a lowermost portion among the gate electrodes, the gate connection portions overlapping the lower isolation region, in a plan-view, and the second dummy channels being arranged on both sides of the lower isolation region in the second direction. ### Claim 3 (depends on 1) The semiconductor device as claimed in claim 1, further comprising: a wiring insulation layer on the channels and the dummy channels; channel plugs passing through the wiring insulation layer to be connected to the channels; and wiring lines electrically connected to the channels through the channel plugs, wherein upper surfaces of the dummy channels are entirely covered with the wiring insulation layer, such that the dummy channels are not electrically connected to the wiring lines. ### Claim 4 (depends on 3) The semiconductor device as claimed in claim 3, wherein each of the wiring lines connects two adjacent channels of the channels along the second direction. ### Claim 5 (depends on 1) The semiconductor device as claimed in claim 1, wherein the dummy channels further include third dummy channels passing through at least a portion of the gate connection portions in the second region, the third dummy channels being arranged between the two columns of the first dummy channels that are adjacent to each other along the first direction. ### Claim 6 (depends on 5) The semiconductor device as claimed in claim 5, wherein the third dummy channels are arranged in a line with the second dummy channels along the second direction. ### Claim 7 (depends on 1) The semiconductor device as claimed in claim 1, wherein: the gate electrodes include contact regions at edges thereof, respectively, a lower gate electrode of the gate electrodes extending farther in the first direction than an upper gate electrode of the gate electrodes, the first dummy channels are at a boundary of the contact regions, and the second dummy channels are in the contact regions. ### Claim 8 (depends on 1) The semiconductor device as claimed in claim 1, further comprising upper isolation regions extending in the first direction, and passing only through some of the gate electrodes, the upper isolation regions passing through at least one gate electrode including a gate electrode in an uppermost portion among the gate electrodes. ### Claim 9 (depends on 1) The semiconductor device as claimed in claim 1, wherein the first region is a memory cell region including a plurality of memory cells along the channels, and the second region is electrically connecting the memory cell region and a control logic region driving the plurality of memory cells. ### Claim 10 (depends on 1) The semiconductor device as claimed in claim 1, wherein the gate connection portions are integrally formed with and include a same material as the subgate electrodes. ### Claim 11 A semiconductor device, comprising: gate electrodes stacked in a direction perpendicular to an upper surface of a substrate, each of the gate electrodes including: subgate electrodes spaced apart from each other, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other; isolation regions extending in a first direction and passing through the gate electrodes, the isolation regions being spaced apart from each other in the first direction, and the gate connection portions being between adjacent ones of the isolation regions; channels extending through the gate electrodes perpendicularly to the upper surface of the substrate; dummy channels extending perpendicularly to the upper surface of the substrate, the dummy channels arranged on at least one side of at least a portion of the gate connections portions in a second direction; a wiring insulation layer on the channels and the dummy channels; wiring lines on the wiring insulation layer, the wiring lines overlapping the channels and at least some of the dummy channels along a vertical direction; and channel plugs passing through the wiring insulation layer and connecting the channels and at least some of the wiring lines, wherein upper surfaces of the dummy channels are entirely covered with the wiring insulation layer, such that the dummy channels are not electrically connected to the wiring lines. ### Claim 12 (depends on 10) The semiconductor device as claimed in claim 10, further comprising a lower isolation region passing through at least one gate electrode including a gate electrode in a lowermost portion among the gate electrodes, the gate connection portions overlapping the lower isolation region, in a plan-view, the dummy channels being arranged on at least one side of the lower isolation region in the second direction. ### Claim 13 A semiconductor device, comprising: a substrate having a first region and a second region; gate electrodes stacked perpendicularly to an upper surface of the substrate in the first region, and extending to different lengths in a first direction in the second region; first isolation regions extended in the first direction while passing through the gate electrodes in the first region and the second region, the first isolation regions being spaced apart from each other in a second direction perpendicular to the first direction; second isolation regions passing through the gate electrodes between the first isolation regions, the second isolation regions being spaced apart from each other in the first direction; channels extending perpendicularly to the upper surface of the substrate through the gate electrodes in the first region; dummy channels extending perpendicularly to the upper surface of the substrate through the gate electrodes in the second region, the dummy channels including first dummy channels arranged in rows and columns and second dummy channels on both sides of a separation region in the second direction, the separation region being a region in which adjacent ones of the second isolation regions are spaced apart from each other in the first direction; upper isolation regions extending in the first direction, and passing through at least one gate electrode including a gate electrode in an uppermost portion among the gate electrodes, between the second isolation regions and the first isolation regions; and a lower isolation region passing only through some of the gate electrodes, the lower isolation region passing at least through one gate electrode including a gate electrode in a lowermost portion among the gate electrodes, in a region vertically overlapping the separation region. ### Claim 14 (depends on 13) The semiconductor device as claimed in claim 13, wherein the second dummy channels are arranged on both sides of the lower isolation region in the second direction. ### Claim 15 (depends on 13) The semiconductor device as claimed in claim 13, wherein the dummy channels further include third dummy channels in the separation region. ### Claim 16 (depends on 15) The semiconductor device as claimed in claim 15, wherein the third dummy channels are arranged in a line with the second dummy channels along the second direction. ### Claim 17 (depends on 13) The semiconductor device as claimed in claim 13, wherein the dummy channels are arranged outside the separation region such that the dummy channels are not disposed within the separation region. ### Claim 18 (depends on 13) The semiconductor device as claimed in claim 13, wherein the second dummy channels are shifted from the columns of the first dummy channels extending in the second direction. ### Claim 19 (depends on 13) The semiconductor device as claimed in claim 13, wherein the second dummy channels are between the rows of the first dummy channels extending in the first direction.