# US 11,114,462 B1 · Three-dimensional memory device with composite charge storage structures and methods for forming the same

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- Number: US 11,114,462 B1
- Document ID: US11114462B1
- Status: Granted
- Kind: B1
- Application number: 16/794,563
- Filed: 2020-02-19
- Published: 2021-08-19
- Granted: 2021-09-07
- Earliest claimed: 2020-02-19
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Zhixin Cui; Ippei Yasuda
- Web page: https://patentgrep.com/patent/US11114462B1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10B 43/10: characterised by the top-view layout
- H10D 64/037: {comprising charge-trapping insulators}
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a composite charge storage structure, a tunneling dielectric layer, and a vertical semiconductor channel. The composite charge storage structure may include a vertical stack of tubular charge storage material portions including a first charge trapping material located at levels of the electrically conductive layers, and a charge storage layer including a second charge trapping material extending through a plurality of electrically conductive layers of the electrically conductive layers. The first charge trapping material has a higher charge trap density than the second charge trapping material. Alternatively, the composite charge storage material portions may include discrete charge storage elements each containing a silicon nitride portion and a silicon carbide nitride liner.

## Claims

### Claim 1

A memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate; and
a memory stack structure extending through the alternating stack, wherein the memory stack structure comprises a vertical stack of discrete charge storage elements that are vertically spaced apart from each other located at levels of the electrically conductive layers, a tunneling dielectric layer located on inner sidewalls of the discrete charge storage elements, and a vertical semiconductor channel contacting an inner sidewall of the tunneling dielectric layer,
wherein each of the discrete charge storage elements comprises:
a silicon nitride portion including an inner sidewall that contacts an outer sidewall of the tunneling dielectric layer; and
a silicon carbide nitride liner in contact with the silicon nitride portion;
further comprising silicon oxide blocking dielectric portions located at each level of the discrete charge storage elements, wherein each of the discrete charge storage elements is laterally spaced from a respective one of the electrically conductive layers by a respective one of the silicon oxide blocking dielectric portions;
wherein each of the discrete charge storage elements further comprises a silicon nitride liner contacting the silicon carbide nitride liner and the outer sidewall of the tunneling dielectric layer;
wherein the silicon nitride liner of each of the discrete charge storage elements contacts a respective overlying one of the insulating layers, and contacts a respective underlying one of the insulating layers; and
wherein the silicon nitride liner of each of the discrete charge storage elements is thinner than the silicon nitride portion.