Three-dimensional memory device with support structures in gate line slits and methods for forming the same

A three-dimensional (3D) memory device, comprising:

• a memory stack comprising interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack;
• a plurality of channel structures extending vertically through the memory stack into a substrate, the plurality of channel structures and the plurality of conductor layers intersecting with one another and forming a plurality of memory cells;
• at least one slit structure extending vertically and laterally in the memory stack and dividing the plurality of memory cells into at least one memory block, the at least one slit structure each comprising a plurality of slit openings and a support structure between adjacent slit openings, the support structure being in contact with adjacent memory blocks and contacting the substrate and comprising a dividing structure over interleaved a plurality of conductor portions and a plurality of insulating portions;
• and
• a source structure comprising an insulating spacer in each of the plurality of slit openings and a source contact in a respective insulating spacer, a top surface of the dividing structure being coplanar with top surfaces of adjacent source contacts in the source structure.

A three-dimensional (3D) memory device, comprising:

• a memory stack comprising interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack;
• a plurality of channel structures extending vertically through the memory stack into a substrate, the plurality of channel structures and the plurality of conductor layers intersecting with one another and forming a plurality of memory cells;
• at least one slit structure extending vertically and laterally in the memory stack and dividing the plurality of memory cells into at least one memory block, the at least one slit structure each comprising a plurality of slit openings and a support structure between adjacent slit openings, the support structure being in contact with adjacent memory blocks and contacting the substrate and comprising a dividing structure over interleaved a plurality of conductor portions and a plurality of insulating portions, a bottom surface of the dividing structure being between a top surface and a bottom surface of a first insulating layer;
• and
• a source structure comprising an insulating spacer in each of the plurality of slit openings and a source contact in a respective insulating spacer.