Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology

A method for forming an integrated circuit, the method comprising:

• doping a substrate to form a first doped well;
• depositing a barrier layer covering the substrate, wherein the barrier layer is dielectric and configured to block oxidants from passing through the barrier layer to the substrate;
• performing a first etch into the barrier layer to form a first opening defined by the barrier layer and laterally spaced from the first doped well;
• doping the substrate through the first opening to form a second doped well laterally spaced from the first doped well while the barrier layer covers the first doped well;
• oxidizing a top surface portion of the substrate in the first opening to form a first gate dielectric layer, wherein the barrier layer blocks oxidants from the oxidizing from reaching the first doped well;
• forming a first gate electrode overlying the second doped well in the first opening, wherein the first gate electrode is formed on the first gate dielectric layer;
• after the forming of the first gate electrode, performing a second etch into the barrier layer to remove a first portion of the barrier layer covering the first doped well;
• and
• forming a second gate electrode overlying the first doped well after the second etch.

A method for forming an integrated circuit, the method comprising:

• depositing a first dielectric layer covering a substrate;
• depositing a seal layer covering the first dielectric layer;
• forming a first opening in and defined by the seal and first dielectric layers to expose a first region of the substrate, but not a second region of the substrate and a third region of the substrate;
• forming a first gate electrode in the first opening and on the first region of the substrate while the seal and first dielectric layers cover the second and third regions of the substrate;
• performing a first etch into the seal layer to remove the seal layer from atop the second and third regions of the substrate, wherein the first etch stops on the first dielectric layer, wherein a dummy portion of the seal layer remains at a periphery of the first region of the substrate upon completion of the first etch;
• after the first etch, forming a second opening in and defined by the first dielectric layer to expose the third region of the substrate, but not the second region of the substrate;
• and
• forming a second gate electrode and a third gate electrode from a common layer and respectively overlying the second and third regions of the substrate, wherein the second gate electrode is separated from the substrate by the first dielectric layer, and wherein the common layer has a bottom recess surrounding the dummy portion before forming the second and third gate electrodes and is distinct from the seal layer.