US 11,114,451 B1Granted

Method of forming a device with FinFET split gate non-volatile memory cells and FinFET logic devices

AssigneeSilicon Storage Technology, Inc.

InventorsFeng Zhou, Xian Liu, JinHo Kim, Serguei Jourba, Catherine Decobert, Nhan Do

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Abstract

A method of forming a device with a silicon substrate having upwardly extending first and second fins. A first implantation forms a first source region in the first silicon fin. A second implantation forms a first drain region in the first silicon fin, and second source and drain regions in the second silicon fin. A first channel region extends between the first source and drain regions. A second channel region extends between the second source and drain regions. A first polysilicon deposition is used to form a floating gate that wraps around a first portion of the first channel region. A second polysilicon deposition is used to form an erase gate wrapping around first source region, a word line gate wrapping around a second portion of the first channel region, and a dummy gate wrapping around the second channel region. The dummy gate is replaced with a metal gate.

Claims18

Dependent claims

A method of forming a device, comprising:

providing a silicon substrate with an upper surface and having first and second areas;
removing portions of the silicon substrate in the first area of the silicon substrate to form an upwardly extending first silicon fin having a pair of side surfaces extending up and terminating at a top surface, and in the second area of the silicon substrate to form an upwardly extending second silicon fin having a pair of side surfaces extending up and terminating at a top surface;
performing a first implantation to form a first source region in the first silicon fin;
performing a second implantation to form a first drain region in the first silicon fin and to form a second source region and a second drain region in the second silicon fin, wherein the first source region and the first drain region define a first channel region of the first silicon fin extending there between, and wherein the second source region and the second drain region define a second channel region of the second silicon fin extending there between;
forming a floating gate disposed over and insulated from a first portion of the first channel region using a first polysilicon deposition, wherein the floating gate wraps around the top and side surfaces of the first silicon fin;
forming an erase gate disposed over and insulated from the first source region, and a word line gate disposed over and insulated from a second portion of the first channel region, and a dummy gate disposed over and insulated from the second channel region, using a second polysilicon deposition, wherein:
the erase gate wraps around the top and side surfaces of the first silicon fin,
the word line gate wraps around the top and side surfaces of the first silicon fin,
the dummy gate wraps around the top and side surfaces of the second silicon fin;
and
replacing the dummy gate with a metal gate that is disposed over and insulated from the second channel region, wherein the metal gate wraps around the top and side surfaces of the second silicon fin.

8 more elements

A method of forming a device, comprising:

providing a silicon substrate with an upper surface and having first and second areas;
removing portions of the silicon substrate in the first area of the silicon substrate to form a plurality of upwardly extending first silicon fins each having a pair of side surfaces extending up and terminating at a top surface, and in the second area of the silicon substrate to form a plurality of upwardly extending second silicon fins each having a pair of side surfaces extending up and terminating at a top surface;
performing a first implantation to form a first source region in each of the first silicon fins;
performing a second implantation to form a first drain region in each of the first silicon fins and to form a second source region and a second drain region in each of the second silicon fins, wherein for each of the first silicon fins the first source region and the first drain region define a first channel region of the first silicon fin extending there between, and wherein for each of the second silicon fins the second source region and the second drain region define a second channel region of the second silicon fin extending there between;
forming a plurality of floating gates each disposed over and insulated from a first portion of one of the first channel regions using a first polysilicon deposition, wherein each of the floating gates wraps around the top and side surfaces of one of the first silicon fins;
forming a plurality of erase gates each disposed over and insulated from one of the first source regions, and a plurality of word line gates each disposed over and insulated from a second portion of one of the first channel regions, and a plurality of dummy gates each disposed over and insulated from one of the second channel regions, using a second polysilicon deposition, wherein:
each of the erase gates wraps around the top and side surfaces of one of the first silicon fins,
each of the word line gates wraps around the top and side surfaces of one of the first silicon fins,
each of the dummy gates wraps around the top and side surfaces of one of the second silicon fins;
and
replacing each of the dummy gates with a metal gate that is disposed over and insulated from one of the second channel regions, wherein each of the metal gates wraps around the top and side surfaces of one of the second silicon fins.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/803,876Filed 27 Feb 2020
Published: US 2021/0272973 A12 Sep 2021
Granted: 7 Sep 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10B 41/43
Simultaneous manufacture of periphery and memory cells: comprising only one type of peripheral transistor
H10B 41/00
Electrically erasable-and-programmable rom [eeprom] devices comprising floating gates
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 41/44
Comprising only one type of peripheral transistor: with a control gate layer also being used as part of the peripheral transistor