# US 11,114,450 B2 · One-time programable memory device having enhanced program efficiency and method for fabricating the same

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- Number: US 11,114,450 B2
- Document ID: US11114450B2
- Status: Granted
- Kind: B2
- Application number: 16/256,589
- Filed: 2019-01-24
- Published: 2019-08-29
- Granted: 2021-09-07
- Earliest claimed: 2018-02-23
- Assignees: SK hynix system ic Inc.
- Applicants: SK hynix system ic Inc.
- Inventors: Kwang Il Choi
- Web page: https://patentgrep.com/patent/US11114450B2

## CPC

- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/60: the control gate being a doped region, e.g. single-poly memory cell
- H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10D 30/0411: {of FETs having floating gates}
- H10D 64/68: characterised by the insulator, e.g. by the gate insulator
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A one-time programmable (OTP) memory device includes a plurality of unit cells which are respectively located at cross points of word lines and bit lines. Each unit cell includes a selection transistor and a storage transistor coupled in series. The selection transistor includes a drain region and a common junction region separated by a first channel region and includes a selection gate structure disposed on the first channel region. The storage transistor includes a source region and the common junction region separated by a second channel region and includes a floating gate structure disposed on the second channel region. A length of an overlapping region between the source region and the floating gate structure in a channel length direction of the storage transistor is less than a length of an overlapping region between the common junction region and the floating gate structure in the channel length direction.

## Claims

### Claim 1

A one-time programmable (OTP) memory device including a plurality of unit cells which are respectively located at cross points of word lines respectively disposed in a plurality of rows and bit lines respectively disposed in a plurality of columns, wherein each of the plurality of unit cells comprising:
a selection transistor comprising a drain region separated from a common junction region by a first channel region, and a selection gate structure disposed over the first channel region; and
a storage transistor comprising a source region separated from the common junction region by a second channel region, and a floating gate structure disposed over the second channel region,
wherein the drain region is coupled to any one of the bit lines,
wherein the source region is coupled to a common source line,
wherein a length of an overlapping region between the source region and the floating gate structure in a channel length direction of the storage transistor is less than a length of an overlapping region between the common junction region and the floating gate structure in the channel length direction of the storage transistor, and
wherein the source region and the common junction region are formed after the floating gate structure and the selection gate structure are formed.

### Claim 2 (depends on 1)

The OTP memory device of claim 1, wherein the selection transistor and the storage transistor include a P-channel MOS transistor structure.

### Claim 3 (depends on 1)

The OTP memory device of claim 1, wherein the drain region and the common junction region include a P-type impurity concentration which is higher than a P-type impurity concentration of the source region.

### Claim 4 (depends on 3)

The OTP memory device of claim 3, further comprising an N-type well region that surrounds bottom surfaces and side surfaces of all of the drain region, the common junction region and the source region.

### Claim 5 (depends on 1)

The OTP memory device of claim 1, wherein each of the common junction region and the source region includes a single junction structure.

### Claim 6 (depends on 1)

The OTP memory device of claim 1, wherein a junction depth of the source region is less than a junction depth of the common junction region.

### Claim 7 (depends on 1)

The OTP memory device of claim 1,
wherein the selection gate structure includes a first gate insulation layer disposed over the first channel region and a selection gate electrode disposed over the first gate insulation layer and coupled to one of the word lines; and
wherein the floating gate structure includes a second gate insulation layer disposed over the second channel region and a floating gate disposed over the second gate insulation layer.

### Claim 8 (depends on 7)

The OTP memory device of claim 7,
wherein the selection transistor and the storage transistor include a P-channel MOS transistor structure; and
wherein the OTP memory device performs a program operation of one selected from the plurality of unit cells if the common source line and one of the word lines are grounded and a positive program voltage is applied to one of the bit lines.

### Claim 9 (depends on 7)

The OTP memory device of claim 7,
wherein the selection transistor and the storage transistor include a P-channel MOS transistor structure; and
wherein the OTP memory device performs a read operation of one selected from the plurality of unit cells if the common source line and one of the word lines are grounded and a positive read voltage is applied to one of the bit lines.

### Claim 10

A one-time programmable (OTP) memory device comprising:
a plurality of active regions extending in a first direction and disposed in a well region to be spaced apart from each other in a second direction intersecting the first direction;
a plurality of selection gate electrodes extending in the second direction to cross the plurality of active regions and being spaced apart from each other in the first direction; and
a plurality of floating gates arrayed in a matrix form to cross the plurality of active regions and to include plural groups of floating gates,
wherein if “i’ is an odd number, an ith selection gate electrode and an (i+1)th selection gate electrode among the plurality of selection gate electrodes are disposed to be adjacent to each other between an ith group of floating gates arrayed in the second direction among the plural groups of floating gates and an (i+1)th group of floating gates arrayed in the second direction among the plural groups of floating gates,
wherein drain regions are respectively disposed in the active regions between the ith selection gate electrode and the (i+1)th selection gate electrode,
wherein common junction regions are respectively disposed in the active regions between each of the plurality of selection gate electrodes and the floating gates adjacent thereto;
wherein source regions are respectively disposed in the active regions between the ith group of floating gates and an (i−1)th group of floating gates among the plural groups of floating gates,
wherein a length of an overlapping region between the source region and the floating gate in the first direction is less than a length of an overlapping region between the common junction region and the floating gate in the first direction, and
wherein the source region and the common junction region are formed after the floating gate structure and the selection gate structure are formed.

### Claim 11 (depends on 10)

The OTP memory device of claim 10,
wherein if “j” is a natural number, a jth active region among the plurality of active regions is shared by unit cells formed in a jth column among a plurality of columns;
wherein a jth selection gate electrode among the plurality of selection gate electrodes is shared by unit cells formed in a jth row among a plurality of rows; and
wherein each of the plurality of floating gates is included in any one of the unit cells.

### Claim 12 (depends on 10)

The OTP memory device of claim 10, wherein the ith selection gate electrode and the (i+1)th selection gate electrode are disposed between an ith floating gate and an (i+1)th floating gate arrayed in the first direction among the plurality of floating gates.

### Claim 13 (depends on 10)

The OTP memory device of claim 10,
wherein an mth selection gate electrode among the plurality of selection gate electrodes is coupled to an mth word line among a plurality of word lines;
wherein all of the drain regions disposed in an nth active region among the plurality of active regions are coupled to an nth bit line among a plurality of bit lines; and
wherein all of the source regions disposed in the plurality of active regions are coupled to a common source line.

### Claim 14 (depends on 13)

The OTP memory device of claim 13,
wherein the well region is an N-type well region;
wherein the drain regions, the common junction regions and the source regions are P-type regions;
wherein the drain regions and the common junction regions have an impurity concentration which is higher than an impurity concentration of the source regions; and
wherein one selected from a plurality of unit cells included in the OTP memory device is programmed by grounding the word line coupled to the selected unit cell and the common source line, by applying a positive program voltage to the bit line coupled to the selected unit cell, by applying a positive program inhibition voltage to the remaining word lines, and by grounding the remaining bit lines.

### Claim 15 (depends on 13)

The OTP memory device of claim 13,
wherein the well region is an N-type well region;
wherein the drain regions, the common junction regions and the source regions are P-type regions;
wherein the drain regions and the common junction regions have an impurity concentration which is higher than an impurity concentration of the source regions; and
wherein a datum stored in one selected from a plurality of unit cells included in the OTP memory device is read out by grounding the word line coupled to the selected unit cell and the common source line and by applying a positive read voltage to the bit line coupled to the selected unit cell.

### Claim 16 (depends on 10)

The OTP memory device of claim 10, wherein each of the common junction regions and the source regions includes a single junction structure.

### Claim 17 (depends on 10)

The OTP memory device of claim 10, wherein a junction depth of the source regions is less than a junction depth of the common junction regions.

### Claim 18

A one-time programmable (OTP) memory device including a plurality of unit cells, each of the plurality of unit cells comprising:
a selection transistor including a drain region separated from a common junction region by a first channel region; and
a storage transistor including a source region separated from the common junction region by a second channel region and a floating gate structure disposed over the second channel region,
wherein a length of an overlapping region between the source region and the floating gate structure of the storage transistor is smaller than a length of an overlapping region between the common junction region and the floating gate structure in the channel length direction of the storage transistor, and
wherein the source region and the common junction region are formed after the floating gate structure and the selection gate structure are formed.

### Claim 19

A one-time programmable (OTP) memory device including a plurality of unit cells which are respectively located at cross points of word lines respectively disposed in a plurality of rows and bit lines respectively disposed in a plurality of columns, wherein each of the plurality of unit cells comprises:
a selection transistor including a drain region separated from a common junction region by a first channel region; and
a storage transistor including a source region separated from the common junction region by a second channel region and a floating gate structure disposed over the second channel region,
wherein the drain region, the common junction region, and the source region are disposed in a well region,
wherein the drain region is coupled to any one of the bit lines,
wherein the source region is coupled to a common source line,
wherein a length of an overlapping region between the source region and the floating gate structure in a channel length direction of the storage transistor is less than a length of an overlapping region between the common junction region and the floating gate structure in the channel length direction of the storage transistor,
wherein the OTP memory device is programmed by applying a ground voltage to the common source line and by applying a positive program voltage to the one of the bit lines and the well region, and
wherein the source region and the common junction region are formed after the floating gate structure and the selection gate structure are formed.