# US 11,114,440 B2 · Semiconductor memory device and method of fabricating the same

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- Number: US 11,114,440 B2
- Document ID: US11114440B2
- Status: Granted
- Kind: B2
- Application number: 16/805,066
- Filed: 2020-02-28
- Published: 2020-06-25
- Granted: 2021-09-07
- Earliest claimed: 2017-11-29
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jungwoo Song; Kwangmin Kim; Jun Ho Lee; Hyuckjin Kang; Yong Kwan Kim; Sangyeon Han; Seguen Park
- Web page: https://patentgrep.com/patent/US11114440B2

## CPC

- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/482: {Bit lines}
- H10B 12/485: {Bit line contacts}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10W 20/48: Insulating materials thereof
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/10: Phase change RAM [PCRAM, PRAM] devices
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

## Claims

### Claim 1

A method of fabricating a semiconductor memory device, the method comprising:
forming on a semiconductor substrate a bit line and a bit line capping pattern on the bit line;
forming a first spacer that covers a sidewall of the bit line capping pattern and a sidewall of the bit line;
forming a lower buried dielectric pattern covering a lower sidewall of the first spacer;
forming a sacrificial spacer and a second spacer that sequentially cover middle and upper sidewalls of the first spacer;
partially removing upper portions of the sacrificial spacer and the second spacer to expose the upper sidewall of the first spacer;
forming a storage node contact adjacent to the second spacer;
forming a conductive layer that covers the bit line capping pattern, the first spacer, the sacrificial spacer, the second spacer, and the storage node contact;
etching the conductive layer to form a recess region exposing the sacrificial spacer and to form a landing pad electrically connected to the storage node contact;
removing the sacrificial spacer to form an air gap region; and
forming an upper buried dielectric pattern that fills the recess region and defines a top end of the air gap region.

### Claim 2 (depends on 1)

The method of claim 1, before the forming of the storage node contact, further comprising forming a third spacer that covers the upper sidewall of the first spacer and a top end of the sacrificial spacer, the conductive layer covering the third spacer,
wherein the forming of the recess region comprises:
providing a first etchant that etches the conductive layer; and
before the third spacer is exposed, providing a second etchant that etches the third spacer.

### Claim 3 (depends on 2)

The method of claim 2,
wherein the forming of the conductive layer comprises:
forming a diffusion barrier layer; and
forming a metal-containing layer on the diffusion barrier layer, and
wherein the forming of the recess region comprises:
providing the first etchant to etch the metal-containing layer until the diffusion barrier layer is exposed; and
after the diffusion barrier layer is exposed, providing a third etchant that etches the diffusion barrier layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the forming of the upper buried dielectric pattern comprises:
forming a first upper buried dielectric pattern that defines the top end of the air gap region; and
forming a second upper buried dielectric pattern that fills the recess region.

### Claim 5 (depends on 4)

The method of claim 4, before the forming of the first upper buried dielectric pattern, further comprising forming a third upper buried dielectric pattern that narrows a width of the top end of the air gap region.

### Claim 6 (depends on 5)

The method of claim 5, wherein the third upper buried dielectric pattern has a density less than a density of the first upper buried dielectric pattern.

### Claim 7 (depends on 5)

The method of claim 5, wherein each of the first and third upper buried dielectric patterns comprises carbon,
wherein a carbon content of the first upper buried dielectric pattern is less than a carbon content of the third upper buried dielectric pattern.

### Claim 8 (depends on 1)

The method of claim 1, before the partially removing of the upper portions of the sacrificial spacer and the second spacer, further comprising forming an insulation fence that limits a position of the storage node contact and is adjacent to the sidewalls of the bit line and the bit line capping pattern,
wherein the upper portions of the sacrificial spacer and the second spacer between the insulation fence and the bit line capping pattern are not etched while partially removing the upper portions of the sacrificial spacer and the second spacer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the first spacer, the sacrificial spacer, and the second spacer are formed to have linear shapes extending along the sidewall of the bit line, in a plan view, and
after the partially removing of the upper portions of the sacrificial spacer and the second spacer, top ends of the sacrificial spacer and the second spacer are higher than a top surface of the bit line.

### Claim 10 (depends on 1)

The method of claim 1, wherein the lower buried dielectric pattern is in contact with a bottom surface of the second spacer.

### Claim 11

A method of fabricating a semiconductor memory device, the method comprising:
forming a semiconductor substrate, a bit line and a bit line capping pattern on the bit line;
forming a first spacer that covers a sidewall of the bit line capping pattern and a sidewall of the bit line;
forming a sacrificial spacer and a second spacer that sequentially cover middle and upper sidewalls of the first spacer;
partially removing upper portions of the sacrificial spacer and the second spacer to expose the upper sidewall of the first spacer;
forming a storage node contact adjacent to the second spacer;
forming a conductive layer that covers the bit line capping pattern, the first spacer, the sacrificial spacer, the second spacer, and the storage node contact;
etching the conductive layer to form a recess region exposing the sacrificial spacer and to form a landing pad electrically connected to the storage node contact;
removing the sacrificial spacer to form an air gap region;
forming a first upper buried dielectric pattern that narrows a width of the top end of the air gap region; and
forming a second upper buried dielectric pattern that defines a top end of the air gap region.

### Claim 12 (depends on 11)

The method of claim 11, further comprising: forming a lower buried dielectric pattern covering a lower sidewall of the first spacer, before forming the sacrificial spacer and the second spacer.

### Claim 13 (depends on 11)

The method of claim 11, before the forming of the storage node contact, further comprising forming a third spacer that covers the upper sidewall of the first spacer and a top end of the sacrificial spacer, the conductive layer covering the third spacer,
wherein the forming of the recess region comprises:
providing a first etchant that etches the conductive layer; and
before the third spacer is exposed, providing a second etchant that etches the third spacer.

### Claim 14 (depends on 13)

The method of claim 13,
wherein the forming of the conductive layer comprises:
forming a diffusion barrier layer; and
forming a metal-containing layer on the diffusion barrier layer, and
wherein the forming of the recess region comprises:
providing the first etchant to etch the metal-containing layer until the diffusion barrier layer is exposed; and
after the diffusion barrier layer is exposed, providing a third etchant that etches the diffusion barrier layer.

### Claim 15 (depends on 11)

The method of claim 11, further comprising: forming a third upper buried dielectric pattern that fills the recess region.

### Claim 16 (depends on 11)

The method of claim 11, before the partially removing of the upper portions of the sacrificial spacer and the second spacer, further comprising forming an insulation fence that limits a position of the storage node contact and is adjacent to the sidewalls of the bit line and the bit line capping pattern,
wherein the upper portions of the sacrificial spacer and the second spacer between the insulation fence and the bit line capping pattern are not etched while partially removing the upper portions of the sacrificial spacer and the second spacer.

### Claim 17

A method of fabricating a semiconductor memory device, the method comprising:
forming a device isolation pattern in a substrate to define an active region;
forming a word line in the device isolation pattern and the substrate, the word line crossing the active region;
forming a word line capping pattern;
forming a first recess region by etching portions of the substrate, the device isolation pattern and the word line capping pattern;
forming a bit line contact in the first recess and forming a bit line on the bit line contact, the bit line crossing over the word line;
forming a lower buried dielectric pattern in the recess region;
forming a sacrificial spacer and a first spacer sequentially covering sidewalls of the bit line;
removing the sacrificial spacer to form an air gap region; and
forming a first upper buried dielectric pattern that defines a top end of the air gap region.

### Claim 18 (depends on 17)

The method of claim 17, wherein the lower buried dielectric pattern is in the word line capping pattern.

### Claim 19 (depends on 17)

The method of claim 17, wherein the word line has a first bottom surface contacting the device isolation pattern and a second bottom surface contacting the substrate, wherein the first bottom surface is lower than the second bottom surface.

### Claim 20 (depends on 17)

The method of claim 17, further comprising a second spacer covering sidewalls of the bit line contact and the bit line before forming the lower buried dielectric pattern.