# US 11,114,434 B2 · Computation-in-memory in three-dimensional memory device

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- Number: US 11,114,434 B2
- Document ID: US11114434B2
- Status: Granted
- Kind: B2
- Application number: 16/542,274
- Filed: 2019-08-15
- Published: 2020-12-31
- Granted: 2021-09-07
- Earliest claimed: 2019-06-28
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Shengwei Yang; Zhongyi Xia; Kun Han
- Web page: https://patentgrep.com/patent/US11114434B2

## CPC

- H10D 88/00: Three-dimensional [3D] integrated devices
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- H10B 43/40: characterised by the peripheral circuit region
- H10F 39/811: {Interconnections}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/951: {Materials of bond pads}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/792: {between multiple chips}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Three-dimensional (3D) memory devices are provided. An exemplary 3D memory device includes a first semiconductor structure including a peripheral circuit, a data processing circuit, and a first bonding layer including a plurality of first bonding contacts. The 3D memory device also includes a second semiconductor structure including an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts. In addition, the 3D memory device includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

## Claims

### Claim 1

A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising a peripheral circuit, a data processing circuit, and a first bonding layer comprising a plurality of first bonding contacts;
a second semiconductor structure comprising an array of 3D NAND memory strings and a second bonding layer comprising a plurality of second bonding contacts; and
a bonding interface between the first bonding layer and the second bonding layer, wherein
the first bonding contacts are in contact with the second bonding contacts at the bonding interface,
the first semiconductor structure is above the second semiconductor structure, and
the first semiconductor structure further comprises a semiconductor layer above the first bonding layer, and a pad-out interconnect layer above the semiconductor layer.

### Claim 2 (depends on 1)

The 3D memory device of claim 1, wherein the semiconductor layer comprises at least one of polysilicon or single-crystal silicon.

### Claim 3 (depends on 1)

The 3D memory device of claim 1, wherein the second semiconductor structure comprises:
a substrate;
a memory stack above the substrate;
the array of 3D NAND memory strings extending vertically through the memory stack; and
the second bonding layer above the memory stack and the array of 3D NAND memory strings.

### Claim 4 (depends on 3)

The 3D memory device of claim 3, wherein in the first semiconductor structure:
the first bonding layer is above the second bonding layer;
the peripheral circuit is above the first bonding layer;
the data processing circuit is above the first bonding layer and non-overlapping with the peripheral circuit; and
the semiconductor layer is above and in contact with the peripheral circuit and the data processing circuit.

### Claim 5 (depends on 1)

The 3D memory device of claim 1, wherein the data processing circuit comprises a field-programmable gate array (FPGA).

### Claim 6 (depends on 1)

The 3D memory device of claim 1, wherein the first semiconductor structure comprises a first interconnect layer vertically between the first bonding layer and the data processing circuit, and the second semiconductor structure comprises a second interconnect layer vertically between the second bonding layer and the array of 3D NAND memory strings.

### Claim 7 (depends on 6)

The 3D memory device of claim 6, wherein the data processing circuit is electrically connected to the array of 3D NAND memory strings through the first and second interconnect layers and the first and second bonding contacts.

### Claim 8 (depends on 1)

The 3D memory device of claim 1, wherein the pad-out interconnect layer comprises one or more interconnects in an interlayer dielectric (ILD) layer.

### Claim 9 (depends on 8)

The 3D memory device of claim 8, wherein the interconnects comprise contact pads.

### Claim 10 (depends on 1)

The 3D memory device of claim 1, wherein the pad-out interconnect layer is configured to transfer electrical signals between the 3D memory device and one or more outside circuits outside the 3D memory device.

### Claim 11 (depends on 10)

The 3D memory device of claim 10, wherein the peripheral circuit and the data processing circuit are electrically connected to the one or more outside circuits through the pad-out interconnect layer.

### Claim 12 (depends on 6)

The 3D memory device of claim 6, wherein the first semiconductor structure further comprises one or more contacts extending through the semiconductor layer to electrically connect the pad-out interconnect layer with the first interconnect layer.

### Claim 13 (depends on 1)

The 3D memory device of claim 1, wherein the peripheral circuit and the data processing circuit are stacked over one another on different planes.

### Claim 14 (depends on 1)

The 3D memory device of claim 1, wherein the array of 3D NAND memory strings comprise a plurality of floating gate NAND memory strings, and the semiconductor layer comprises a source plate of the plurality of floating gate NAND memory strings.