# US 11,114,433 B2 · 3DIC structure and method of fabricating the same

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- Number: US 11,114,433 B2
- Document ID: US11114433B2
- Status: Granted
- Kind: B2
- Application number: 16/035,702
- Filed: 2018-07-15
- Published: 2020-01-16
- Granted: 2021-09-07
- Earliest claimed: 2018-07-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsien-Wei Chen; Ming-Fa Chen
- Web page: https://patentgrep.com/patent/US11114433B2

## CPC

- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 20/082: {the openings being tapered via holes}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/30: Die-attach connectors
- H10W 72/90: Bond pads, in general
- H10W 90/00: Package configurations
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/655: Fan-out layouts
- H10W 72/01931: {using blanket deposition}
- H10W 72/01953: {by etching}
- H10W 72/0198: {batch processes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/853: {On the same surface}
- H10W 72/874: {On different surfaces}
- H10W 72/936: {Multiple bond pads having different shapes}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/9413: {on encapsulations}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/957: {Multiple bond pads having different materials}
- H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/334: {Thermocompression bonding}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a three dimensional integrated circuit (3DIC) structure including a first die, a second die, and a hybrid bonding structure bonding the first die and the second die. The hybrid bonding structure includes a first bonding structure and a second bonding structure. The first bonding structure includes a first bonding dielectric layer and a first bonding metal layer. The first bonding metal layer is disposed in the first bonding dielectric layer. The first bonding metal layer includes a first via plug and a first metal feature disposed over the first via plug, wherein a height of the first metal feature is greater than or equal to a height of the first via plug. A method of fabricating the 3DIC structure is also provided.

## Claims

### Claim 1

A three dimensional integrated circuit (3DIC) structure, comprising:
a first die having a first interconnect structure and a first pad electrically connected to the first interconnect structure;
a second die having a second interconnect structure and a second pad electrically connected to the second interconnect structure; and
a hybrid bonding structure bonding the first die and the second die, and disposed between the first interconnect structure and the second interconnect structure, wherein the hybrid bonding structure comprises a first bonding structure covering the first pad and a second bonding structure covering the second pad, the first bonding structure comprises:
a first bonding dielectric layer; and
a first bonding metal layer, disposed in the first bonding dielectric layer, wherein the first bonding metal layer comprises a first via plug and a first metal feature disposed over and in direct contact with the first via plug, a height of the first metal feature is greater than a height of the first via plug,
wherein the first pad is laterally aside the first bonding metal layer, and separated from the second pad by the first bonding dielectric layer therebetween, and a bottom surface of the first metal feature contacting the first via plug is lower than a top surface of the first pad of the first die.

### Claim 2 (depends on 1)

The 3DIC structure of claim 1, wherein a resistance of the first metal feature is lower than a resistance of the first via plug.

### Claim 3 (depends on 1)

The 3DIC structure of claim 1, wherein the first bonding dielectric layer comprises:
a first bonding dielectric material conformally covering the first die; and
a second bonding dielectric material, disposed over the first bonding dielectric material, wherein a thickness of the second bonding dielectric material is greater than or equal to a thickness of the first bonding dielectric material,
wherein the first metal feature penetrates the second bonding dielectric material and partially into the first bonding dielectric material, and the first via plug is formed in the first bonding dielectric material.

### Claim 4 (depends on 3)

The 3DIC structure of claim 3, wherein the first bonding dielectric material and the second bonding dielectric material have different materials.

### Claim 5 (depends on 3)

The 3DIC structure of claim 3, wherein the first bonding dielectric layer further comprises a blocking layer between the first bonding dielectric material and the second bonding dielectric material, the blocking layer conformally covers the first bonding dielectric material.

### Claim 6 (depends on 5)

The 3DIC structure of claim 5, wherein the blocking layer and the first bonding dielectric material have different materials, and the blocking layer and the second bonding dielectric material have different materials.

### Claim 7

A three dimensional integrated circuit (3DIC) structure, comprising:
a first die having a first pad and a second die having a second pad;
a hybrid bonding structure bonding the first die and the second die, wherein the hybrid bonding structure comprises:
a dielectric layer between the first die and the second die; and
a conductive feature disposed in the dielectric layer, wherein the conductive feature comprises:
a first via plug electrically connected to the first die;
a second via plug electrically connected to the second die; and
a middle portion electrically connected to the first via plug and the second via plug, wherein the middle portion is disposed between and in direct contact with the first via plug and the second via plug,
wherein the first pad is separated from the second pad by a portion of the dielectric layer, and a height of the middle portion is greater than a distance between the first pad of the first die and the second pad of the second die.

### Claim 8 (depends on 7)

The 3DIC structure of claim 7, wherein the height of the middle portion is greater than or equal to a sum height of the first via plug and the second via plug.

### Claim 9 (depends on 7)

The 3DIC structure of claim 7, wherein the dielectric layer comprises:
a first dielectric material, conformally covering the first die;
a second dielectric material conformally covering the second die; and
a third dielectric material disposed between the first dielectric material and the second dielectric material,
wherein the middle portion penetrates the third dielectric material and partially into the first dielectric material and the second dielectric material, the first via plug is formed in the first dielectric material, and the second via plug is formed in the second dielectric material.

### Claim 10 (depends on 9)

The 3DIC structure of claim 9, wherein a thickness of the third dielectric material is greater than or equal to a sum thickness of the first dielectric material and the second dielectric material.

### Claim 11 (depends on 9)

The 3DIC structure of claim 9, wherein the hybrid bonding structure further comprises a blocking layer disposed between the first dielectric material and the third dielectric material and between the second dielectric material and the third dielectric material.

### Claim 12 (depends on 9)

The 3DIC structure of claim 9, wherein the first pad, the second pad, and the hybrid bonding structure are located between and electrically connected to a first interconnect structure of the first die and a second interconnect structure of the second die.

### Claim 13 (depends on 9)

The 3DIC structure of claim 9, further comprising:
a first dummy metal feature disposed in and exposed by the first dielectric material over the first pad of the first die,
a second dummy metal feature disposed in and exposed by the second dielectric material over the second pad of the second die,
wherein the first dummy metal feature and the second dummy metal feature are bonded together and a sum height of the first and second dummy metal features is less than the height of the middle portion.

### Claim 14

A method of fabricating a three dimensional integrated circuit (3DIC) structure, comprising:
forming a first die, comprising:
forming a first interconnect structure over a substrate;
forming a first pad over the first interconnect structure, wherein the first pad is electrically connected to the first interconnect structure;
bonding the first die to a second die having a second interconnect structure and a second pad electrically connected to the second interconnect structure through a hybrid bonding structure, wherein the hybrid bonding structure is disposed between the first interconnect structure and the second interconnect structure, the hybrid bonding structure comprises a first bonding structure covering the first pad and a second bonding structure covering the second pad, wherein foi ming the first bonding structure comprises:
forming a bonding dielectric layer over the first interconnect structure; and
forming a bonding metal layer in the bonding dielectric layer to electrically connect to the first interconnect structure, wherein the bonding metal layer comprises a via plug and a metal feature formed over and in direct contact with the via plug, a height of the metal feature is greater than a height of the via plug,
wherein the first pad is laterally aside the bonding metal layer, and separated from the second pad by the bonding dielectric layer therebetween, and a bottom surface of the metal feature contacting the via plug is lower than a top surface of the first pad of the first die.

### Claim 15 (depends on 14)

The method of claim 14, wherein the forming the bonding dielectric layer over the first interconnect structure comprises:
forming a first bonding dielectric material to confonnally cover the first pad and the first interconnect structure;
forming a blocking layer confomally over the first bonding dielectric material; and
forming a second bonding dielectric material over the blocking layer, wherein the blocking layer and the first bonding dielectric material have different materials, and the blocking layer and the second bonding dielectric material have different materials.

### Claim 16 (depends on 15)

The method of claim 15, wherein a thickness of the second bonding dielectric material is greater than or equal to a thickness of the first bonding dielectric material.

### Claim 17 (depends on 16)

The method of claim 16, wherein the forming the bonding metal layer in the bonding dielectric layer comprises:
forming a first resist pattern over the substrate;
removing a portion of the second bonding dielectric material by using the blocking layer as an etching stop layer and by using the first resist pattern as a mask to form an opening;
forming a second resist pattern over the substrate;
removing a portion of the first bonding dielectric material by using the second resist pattern as a mask to form a via hole, wherein a depth of the opening is greater than or equal to a depth of the via hole; and
filling the opening and the via hole with a conductive material to form the metal feature in the opening and form the via plug in the via hole.

### Claim 18 (depends on 14)

The method of claim 14, wherein the forming the bonding dielectric layer over the first interconnect structure comprises:
forming a first bonding dielectric material to conformally cover the first pad and the first interconnect structure; and
forming a second bonding dielectric material over the first bonding dielectric material, wherein the first bonding dielectric material and the second bonding dielectric material have different materials and a thickness of the second bonding dielectric material is greater than or equal to a thickness of the first bonding dielectric material.

### Claim 19 (depends on 18)

The method of claim 18, wherein the forming the bonding metal layer in the bonding dielectric layer comprises:
forming a first resist pattern over the substrate;
removing a portion of the second bonding dielectric material by using the first bonding dielectric material as an etching stop layer and by using the first resist pattern as a mask to form an opening;
forming a second resist pattern over the substrate;
removing a portion of the first bonding dielectric material by using the second resist pattern as a mask to form a via hole, wherein a depth of the opening is greater than or equal to a depth of the via hole; and
filling the opening and the via hole with a conductive material to form the metal feature in the opening and form the via plug in the via hole.

### Claim 20 (depends on 14)

The method of claim 14, wherein the forming the metal feature over the via plug further comprises forming a dummy metal feature over the first pad on the first interconnect structure simultaneously, wherein a height of the dummy metal feature is less than the height of the metal feature.