# US 11,114,428 B2 · Integrated circuit device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,114,428 B2 - Document ID: US11114428B2 - Status: Granted - Kind: B2 - Application number: 16/806,030 - Filed: 2020-03-02 - Published: 2021-03-04 - Granted: 2021-09-07 - Earliest claimed: 2019-08-30 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Chanho Kim; Dongku Kang; Daeseok Byeon - Web page: https://patentgrep.com/patent/US11114428B2 ## CPC - H10W 90/00: Package configurations - H10B 43/40: characterised by the peripheral circuit region - H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes} - H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers} - H10W 80/00: Direct bonding of chips, wafers or substrates - H10B 43/10: characterised by the top-view layout - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10W 72/07236: {Soldering or alloying} - H10W 72/921: {Structures or relative sizes of bond pads} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/792: {between multiple chips} - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES ## Abstract An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction. ## Claims ### Claim 1 An integrated circuit device comprising: a memory comprising a memory stack, a memory cell interconnection comprising a plurality of upper conductive patterns configured to be electrically connectable to the memory stack, and a memory cell insulation surrounding the memory stack and the memory cell interconnection; a peripheral circuit comprising a peripheral circuit board, a peripheral circuit region on the peripheral circuit board, and a peripheral circuit interconnection comprising a plurality of lower conductive patterns between the peripheral circuit region and the memory and bonded to the memory cell interconnection; a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, the plurality of conductive bonding structures being bonded plurality of first upper conductive patterns selected from among the plurality of upper conductive patterns and a respective plurality of first lower conductive patterns selected from among the plurality of lower conductive patterns; and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a second lower conductive pattern selected from among the plurality of lower conductive patterns in the vertical direction, in a second region, the second region overlapping the memory cell insulation in the vertical direction. ### Claim 2 (depends on 1) The integrated circuit device of claim 1, wherein the through electrode penetrates the memory cell insulation and extends to the second lower conductive pattern. ### Claim 3 (depends on 1) The integrated circuit device of claim 1, wherein the through electrode penetrates the peripheral circuit board and the peripheral circuit region and extends to the second lower conductive pattern. ### Claim 4 (depends on 1) The integrated circuit device of claim 1, wherein the first lower conductive pattern and the second lower conductive pattern are at different levels. ### Claim 5 (depends on 1) The integrated circuit device of claim 1, wherein the first lower conductive pattern and the second lower conductive pattern are at the same level. ### Claim 6 (depends on 1) The integrated circuit device of claim 1, wherein the first lower conductive pattern and the second lower conductive pattern comprise different metals. ### Claim 7 (depends on 1) The integrated circuit device of claim 1, wherein the first lower conductive pattern and the second lower conductive pattern comprise the same metal. ### Claim 8 (depends on 1) The integrated circuit device of claim 1, wherein each of the first lower conductive pattern and the second lower conductive pattern has a shape in which a width in a horizontal direction increases as the first lower conductive pattern and the second lower conductive pattern respectively becomes closer toward the memory. ### Claim 9 (depends on 1) The integrated circuit device of claim 1, wherein the first lower conductive pattern has a shape in which a width in a horizontal direction increases as the first lower conductive pattern becomes closer toward the memory, and the second lower conductive pattern has a shape in which a width in the horizontal direction decreases as the second lower conductive pattern becomes closer toward the memory. ### Claim 10 (depends on 1) The integrated circuit device of claim 1, further comprising a conductive pad in contact with the through electrode and extending in a horizontal direction outside of the memory, wherein the conductive pad comprises a portion overlapping the memory stack in the vertical direction. ### Claim 11 (depends on 1) The integrated circuit device of claim 1, further comprising a conductive pad in contact with the through electrode and extending in a horizontal direction outside of the peripheral circuit, wherein the conductive pad is spaced apart from the peripheral circuit region with the peripheral circuit board therebetween. ### Claim 12 An integrated circuit device comprising: a memory comprising a memory stack comprising a plurality of bit lines extending in a first horizontal direction, a memory cell interconnection comprising a plurality of upper conductive patterns configured to be electrically connectable to the plurality of bit lines, and a memory cell insulation surrounding the memory stack and the memory cell interconnection; a peripheral circuit comprising a peripheral circuit board, a peripheral circuit region on the peripheral circuit board, and a peripheral circuit interconnection comprising a plurality of lower conductive patterns between the peripheral circuit region and the memory and bonded to the memory cell interconnection; a conductive bonding on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, the conductive bonding being bonded first upper conductive pattern selected from among the plurality of upper conductive patterns and a first lower conductive pattern selected from among the plurality of lower conductive patterns; and a plurality of through electrodes extended in the vertical direction through one of the memory cell insulation and the peripheral circuit board, in a second region spaced apart from the first region in a horizontal direction, wherein the plurality of through electrodes comprise a plurality of first through electrodes arranged in a line along the first horizontal direction in the second region. ### Claim 13 (depends on 12) The integrated circuit device of claim 12, wherein the plurality of through electrodes further comprise a plurality of second through electrodes arranged in a line along a second horizontal direction perpendicular to the first horizontal direction in the second region. ### Claim 14 (depends on 12) The integrated circuit device of claim 12, wherein the plurality of through electrodes comprise one through electrode in contact with a second lower conductive pattern selected from among the plurality of lower conductive patterns, and the one through electrode extends to the second lower conductive pattern through the memory cell insulation. ### Claim 15 (depends on 12) The integrated circuit device of claim 12, wherein the plurality of through electrodes comprise one through electrode in contact with a second lower conductive pattern selected from among the plurality of lower conductive patterns, and the one through electrode extends to the second lower conductive pattern through the peripheral circuit board and the peripheral circuit region. ### Claim 16 (depends on 15) The integrated circuit device of claim 15, wherein a first shortest distance from the peripheral circuit board to the first lower conductive pattern is greater than a second shortest distance from the peripheral circuit board to the second lower conductive pattern. ### Claim 17 (depends on 15) The integrated circuit device of claim 15, wherein a first shortest distance from the peripheral circuit board to the first lower conductive pattern is the same as a second shortest distance from the peripheral circuit board to the second lower conductive pattern. ### Claim 18 (depends on 15) The integrated circuit device of claim 15, wherein the first lower conductive pattern and the second lower conductive pattern comprise different metals. ### Claim 19 An integrated circuit device comprising: a memory comprising a semiconductor layer, a memory stack on the semiconductor layer, a memory cell interconnection comprising a plurality of upper conductive patterns overlapping the memory stack in a vertical direction and configured to be electrically connectable to the memory stack, and a memory cell insulation surrounding the semiconductor layer, the memory stack, and the memory cell interconnection; a peripheral circuit comprising a peripheral circuit board, a peripheral circuit region on the peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory and bonded to the memory cell interconnection; a plurality of conductive bonding structures comprising Cu and on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in the vertical direction; a plurality of lower conductive patterns comprising at least one metal selected from among Al, W, and Cu and in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction; and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board in the second region and contacting one lower conductive pattern among the plurality of lower conductive patterns. ### Claim 20 (depends on 19) The integrated circuit device of claim 19, wherein the plurality of lower conductive patterns comprise a first lower conductive pattern constituting the plurality of conductive bonding structures and a second lower conductive pattern in contact with the through electrode, the first lower conductive pattern has a shape in which a width in a horizontal direction increases as the first lower conductive pattern becomes closer toward the memory, and the second lower conductive pattern has a shape in which a width in the horizontal direction decreases as the second lower conductive pattern becomes closer toward the memory.