# US 11,114,427 B2 · 3D semiconductor processor and memory device and structure

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- Number: US 11,114,427 B2
- Document ID: US11114427B2
- Status: Granted
- Kind: B2
- Application number: 16/786,060
- Filed: 2020-02-10
- Published: 2020-06-11
- Granted: 2021-09-07
- Earliest claimed: 2015-11-07
- Assignees: Monolithic 3D Inc.
- Applicants: Monolithic 3D Inc.
- Inventors: Zvi Or-Bach; Jin-Woo Han
- Web page: https://patentgrep.com/patent/US11114427B2

## CPC

- H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60)
- H10W 90/00: Package configurations
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/20: Configurations of stacked chips
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A 3D semiconductor device, the device including: a first level including first single crystal transistors; and a second level including second single crystal transistors, where the first level is overlaid by the second level, where a vertical distance from the first single crystal transistors to the second single crystal transistors is less than four microns, where the first level includes a plurality of processors, and where the second level includes a plurality of memory cells.

## Claims

### Claim 1

A 3D semiconductor device, the device comprising:
a first level comprising first single crystal transistors; and
a second level comprising second single crystal transistors,
wherein said first level is overlaid by said second level,
wherein a vertical distance from said first single crystal transistors to said second single crystal transistors is less than four microns,
wherein said first level comprises a plurality of processors, and
wherein said second level comprises a plurality of memory cells.

### Claim 2 (depends on 1)

The 3D semiconductor device according to claim 1,
wherein at least one of said memory cells is a charge trap type memory cell.

### Claim 3 (depends on 1)

The 3D semiconductor device according to claim 1,
wherein said second level is a layer transferred and bonded level.

### Claim 4 (depends on 1)

The 3D semiconductor device according to claim 1,
wherein said second level is customized for a specific application from a generic level.

### Claim 5 (depends on 1)

The 3D semiconductor device according to claim 1, further comprising:
first vertical connections and second vertical connections for connecting said first transistors to said second transistors,
wherein said plurality of processors comprise a first processor and a second processor,
wherein said first processor is connected to said first vertical connections, and
wherein said second processor is connected to said second vertical connections.

### Claim 6 (depends on 1)

The 3D semiconductor device according to claim 1, further comprising:
memory control lines,
wherein each of said plurality of memory cells are controlled directly by at least two of said memory control lines.

### Claim 7 (depends on 1)

The 3D semiconductor device according to claim 1,
wherein said plurality of processors comprise at least four processors.

### Claim 8

A 3D semiconductor device, the device comprising:
a first level comprising first single crystal transistors; and
a second level comprising second single crystal transistors,
wherein said first level is overlaid by said second level,
wherein a vertical distance from said first single crystal transistors to said second single crystal transistors is less than four microns,
wherein said first level comprises at least one processor,
wherein said second level comprises a plurality of memory cells, and
wherein at least one of said memory cells is flash type memory cell.

### Claim 9 (depends on 8)

The 3D semiconductor device according to claim 8,
wherein said first level comprises at least four processors.

### Claim 10 (depends on 8)

The 3D semiconductor device according to claim 8,
wherein said second level is a layer transferred and bonded level.

### Claim 11 (depends on 8)

The 3D semiconductor device according to claim 8,
wherein said second level is customized for a specific application from a generic level.

### Claim 12 (depends on 8)

The 3D semiconductor device according to claim 8, further comprising:
first vertical connections and second vertical connections for connecting said first transistors to said second transistors,
wherein said first level comprises at least two processors,
wherein said at least two processors comprise a first processor and a second processor,
wherein said first processor is connected to said first vertical connections, and
wherein said second processor is connected to said second vertical connections.

### Claim 13 (depends on 8)

The 3D semiconductor device according to claim 8, further comprising:
memory control lines,
wherein each of said plurality of memory cells are controlled directly by at least two of said memory control lines.

### Claim 14 (depends on 8)

The 3D semiconductor device according to claim 8,
wherein said at least one of said memory cells is a charge trap type memory.

### Claim 15

A 3D semiconductor device, the device comprising:
a first level comprising first single crystal transistors; and
a second level comprising second single crystal transistors,
wherein said first level is overlaid by said second level,
wherein a vertical distance from said first single crystal transistors to said second single crystal transistors is less than four microns,
wherein said first level comprises at least one processor,
wherein said second level comprises a plurality of memory cells, and
wherein said second level is a layer transferred and bonded level.

### Claim 16 (depends on 15)

The 3D semiconductor device according to claim 15,
wherein at least one of said memory cells is a charge trap type memory cell.

### Claim 17 (depends on 15)

The 3D semiconductor device according to claim 15,
wherein said first level comprises at least four processors.

### Claim 18 (depends on 15)

The 3D semiconductor device according to claim 15,
wherein said second level is customized for a specific application from a generic level.

### Claim 19 (depends on 15)

The 3D semiconductor device according to claim 15, further comprising:
first vertical connections and second vertical connections for connecting said first transistors to said second transistors,
wherein said first level comprises at least two processors,
wherein said at least two processors comprise a first processor and a second processor,
wherein said first processor is connected to said first vertical connections, and
wherein said second processor is connected to said second vertical connections.

### Claim 20 (depends on 15)

The 3D semiconductor device according to claim 15, further comprising:
memory control lines,
wherein each of said plurality of memory cells are controlled directly by at least two of said memory control lines.