# US 11,114,417 B2 · Through-silicon via (TSV) test circuit, TSV test method and integrated circuits (IC) chip

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- Number: US 11,114,417 B2
- Document ID: US11114417B2
- Status: Granted
- Kind: B2
- Application number: 16/950,020
- Filed: 2020-11-17
- Published: 2021-03-11
- Granted: 2021-09-07
- Earliest claimed: 2018-09-05
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: You-Hsien Lin
- Web page: https://patentgrep.com/patent/US11114417B2

## CPC

- H10W 90/00: Package configurations
- G01R 31/2853: {Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66)}
- G01R 31/31717: {Interconnect testing (by scan techniques see G01R31/31855)}
- G01R 31/318505: {Test of Modular systems, e.g. Wafers, MCM's}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 90/284: {characterised by structural arrangements for measuring or testing}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit (IC) with a TSV test circuit, a TSV test method are provided, pertaining to IC technologies. The IC may include a first TSV, a second TSV and a phase detector. A first end of the first TSV may be coupled to a predetermined signal output, and a second end of the first TSV may be coupled to a first end of the second TSV. A second end of the second TSV may be coupled to a first input of the phase detector, and a second input of the phase detector may be coupled to the predetermined signal output. The phase detector may be configured to determine a phase difference between signals at the first and the second inputs. In this IC, a defective TSV can be identified and segregated with a redundant TSV. This IC facilitates efficient fault correction and signal routing in the IC.

## Claims

### Claim 1

An integrated circuit (IC) with a through-silicon via (TSV) test circuit, comprising a first TSV, a second TSV and a phase detector,
a first end of the first TSV coupled to a predetermined signal output, and a second end of the first TSV coupled to a first end of the second TSV,
a second end of the second TSV coupled to a first input of the phase detector,
a second input of the phase detector coupled to the predetermined signal output,
wherein the phase detector is configured to determine a phase difference between a signal at the first input of the phase detector and a signal at the second input of the phase detector, and wherein a test result is determined by comparing the phase difference with a predetermined threshold,
wherein a stacked tier associated with the second end of the first TSV comprises a phase calibrator configured to apply a delay compensation to an operational signal output from the second end of the first TSV based on the phase difference output from the phase detector.

### Claim 2 (depends on 1)

The IC of claim 1, wherein each of the first and the second TSVs connects two or more stacked tiers.

### Claim 3

An integrated circuit (IC) with a through-silicon via (TSV) test circuit, comprising a first TSV, a second TSV and a phase detector,
a first end of the first TSV coupled to a predetermined signal output, and a second end of the first TSV coupled to a first end of the second TSV,
a second end of the second TSV coupled to a first input of the phase detector,
a second input of the phase detector coupled to the predetermined signal output,
wherein the phase detector is configured to determine a phase difference between a signal at the first input of the phase detector and a signal at the second input of the phase detector, and wherein a test result is determined by comparing the phase difference with a predetermined threshold,
a first selector and a first distributor, the first selector comprising a first input, a second input, a control terminal and an output, the first distributor comprising an input, a control terminal, a first output and a second output,
the first input of the first selector configured to receive a first operational signal to be input to the first TSV, the second input of the first selector coupled to the predetermined signal output, the control terminal of the first selector configured to receive a first test control signal, the output of the first selector coupled to the first end of the first TSV,
the input of the first distributor coupled to the second end of the first TSV, the control terminal of the first distributor configured to receive the first test control signal, the first output of the first distributor coupled to the first end of the second TSV, the second output of the first distributor coupled to an active component associated with the first operational signal.

### Claim 4 (depends on 3)

The IC of claim 3, further comprising:
a third TSV, a first end of the third TSV coupled to the predetermined signal output, a second end of the third TSV coupled to the first end of the second TSV.

### Claim 5 (depends on 4)

The IC of claim 4, further comprising:
a second selector and a second distributor, the second selector comprising a first input, a second input, a control terminal and an output, the second distributor comprising an input, a control terminal, a first output and a second output,
the first input of the second selector configured to receive a second operational signal to be input to the third TSV, the second input of the second selector coupled to the predetermined signal output, the control terminal of the second selector configured to receive a second test control signal, the output of the second selector coupled to the first end of the third TSV,
the input of the second distributor coupled to the second end of the third TSV, the control terminal of the second distributor configured to receive the second test control signal, the first output of the second distributor coupled to the first end of the second TSV, the second output of the second distributor coupled to an active component associated with the second operational signal.

### Claim 6 (depends on 5)

The IC of claim 5, further comprising:
a third selector and a fourth selector, each of the third and the fourth selectors comprising a first input, a second input, a control terminal and an output,
the first input of the third selector coupled to the output of the first selector, the second input of the third selector coupled to the output of the second selector, the control terminal of the third selector configured to receive a third test control signal, the output of the third selector coupled to the second input of the phase detector,
the first input of the fourth selector coupled to the first output of the first distributor, the second input of the fourth selector coupled to the first output of the second distributor, the control terminal of the fourth selector configured to receive a fourth test control signal, the output of the fourth selector coupled to the first end of the second TSV.

### Claim 7 (depends on 4)

The IC of claim 4, further comprising:
one or more additional TSVs, each of the one or more additional TSVs having a first end coupled to the predetermined signal output and a second end coupled to the first end of the second TSV.

### Claim 8 (depends on 1)

The IC of claim 1, wherein the stacked tier associated with the second end of the first TSV comprises a delay-locked loop,
and wherein the delay-locked loop is configured to apply a delay compensation to an operational signal output from the second end of the first TSV based on the phase difference output from the phase detector.

### Claim 9

A through-silicon via (TSV) test method, comprising:
inputting a predefined signal to a phase detector, the predefined signal being a first signal wherein the phase detector comprises a first input and a second input, and the first signal is input to the second input of the phase detector;
inputting the predefined signal, as an input signal of a first TSV, to the first TSV, wherein the first TSV is the TSV whose working condition to be tested;
inputting, via a second TSV, an output signal from the first TSV to the phase detector, the output signal from the first TSV being a second signal, wherein the second signal is input to the first input of the phase detector;
determining, by the phase detector, a phase difference between the first signal and the second signal;
determining a test result by comparing the phase difference with a predetermined threshold;
transmitting, in response to the input signal of the first TSV being an operational signal, the phase difference between the first signal and the second signal to a phase calibrator in a stacked tier associated with a second end of the first TSV; and
applying, by the phase calibrator, a delay compensation to the operational signal.

### Claim 10 (depends on 9)

The method of claim 9, wherein the inputting the predefined signal to the first TSV comprises:
inputting, in response to a first test control signal, the predefined signal to the first TSV,
and wherein the inputting, via a second TSV, an output signal from the first TSV to the phase detector comprises:
inputting, in response to the first test control signal and via the second TSV, the output signal from the first TSV to the phase detector.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
inputting the predefined signal to a third TSV;
inputting, via the second TSV, an output signal from the third TSV to the phase detector, the output signal from the third TSV being a third signal; and
determining, by the phase detector, a phase difference between the first signal and the third signal.

### Claim 12 (depends on 11)

The method of claim 11, wherein the inputting the predefined signal to a third TSV comprises:
inputting, in response to a second test control signal, the predefined signal to the third TSV, and wherein the inputting, via the second TSV, an output signal from the third TSV to the phase detector comprises:
inputting, in response to the second test control signal and via the second TSV, the output signal from the third TSV to the phase detector.

### Claim 13 (depends on 9)

The method of claim 9, further comprising:
transmitting, in response to the input signal of the first TSV being an operational signal, the phase difference between the first signal and the second signal to a delay-locked loop in the stacked tier associated with a second end of the first TSV; and
applying, by the delay-locked loop, a delay compensation to the operational signal.