# US 11,114,415 B2 · Semiconductor device with a layered protection mechanism and associated systems, devices, and methods

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- Number: US 11,114,415 B2
- Document ID: US11114415B2
- Status: Granted
- Kind: B2
- Application number: 16/823,028
- Filed: 2020-03-18
- Published: 2020-07-09
- Granted: 2021-09-07
- Earliest claimed: 2018-01-24
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Wei Zhou; Bret K. Street
- Web page: https://patentgrep.com/patent/US11114415B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 40/10: Arrangements for heating
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10W 70/421: {Shapes or dispositions}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 76/43: Gaseous fillings
- H10W 42/271: {the arrangements being between stacked chips}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 72/016: {of strap connectors}
- H10W 72/07188: {Apparatus chuck}
- H10W 72/072: {of bump connectors}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07323: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/07331: {Connecting techniques}
- H10W 72/07332: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting}
- H10W 72/07341: {Controlling the bonding environment, e.g. atmosphere composition or temperature}
- H10W 72/07354: {changes in dispositions}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/324: {Die-attach connectors having multiple side-by-side cores}
- H10W 72/331: {Shapes of die-attach connectors}
- H10W 72/332: {Plan-view shape, i.e. in top view}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/348: {Top-view layouts, e.g. mirror arrays}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/354: {comprising polymers}
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 80/314: {characterized by direct bonding of pads or other interconnections}
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 95/00: Packaging processes not covered by the other groups of this subclass
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first die; a second die attached over the first die; a metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level; wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.

## Claims

### Claim 1

A semiconductor device, comprising:
a first die;
a second die attached over the first die;
a first metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and
a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level;
wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first metal enclosure and the second metal enclosure do not directly contact each other.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first metal enclosure and the second metal enclosure are separated by an enclosure separation distance, wherein the enclosure separation distance correlates to the enclosure capacitance.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the enclosure separation distance is uniform between the first metal enclosure and the second metal enclosure.

### Claim 5 (depends on 2)

The semiconductor device of claim 2, wherein the first metal enclosure and the second metal enclosure form an enclosure separation space between the first die and the second die, wherein the enclosure separation space continuously encircles a set of one or more internal interconnects, wherein the enclosure separation space is vacuum, filled with a gas, or filled with a dielectric material.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the first die and the second die are singulated semiconductor dies that comprise a die stack.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein:
the second metal enclosure is an outer enclosure that encircles an overall enclosed space;
the first metal enclosure is a first inner enclosure that encircles a first inner space; and further comprising:
a second inner enclosure directly contacting and vertically extending between the first die and the second die, wherein the second inner enclosure peripherally encircles a second inner space that is within the overall enclosed space and mutually exclusive from the first inner space.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising:
a third die attached over the second die;
an upper-level inner enclosure directly contacting and vertically extending between the second die and the third die and configured to electrically connect to the first voltage level; and
an upper-level outer enclosure directly contacting and vertically extending between the second die and the third die, wherein the upper-level outer enclosure peripherally encircles the upper-level inner enclosure and is configured to electrically connect to the second voltage level.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein:
one or more points, surfaces, or portions on each of the upper-level inner enclosure and the lower-level inner enclosure are coincident along a first vertical line; and
one or more points, surfaces, or portions on each of the upper-level outer enclosure and the lower-level outer enclosure are coincident along a second vertical line.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein;
the second metal enclosure is an outer-most enclosure along a horizontal direction; and
the second metal enclosure is electrically coupled to electrical ground.

### Claim 11

A semiconductor device including a die stack having at least two dies, comprising:
a plurality of interconnects electrically coupling two or more adjacent dies of the die stack; and
a first metal sealing member and a second metal sealing member disposed between a pair of adjacent dies, wherein
the first metal sealing member is configured to connect to a first voltage level,
the second metal sealing member is configured to connect to a second voltage level, and
the first metal sealing member encloses one or more interconnects and is nested within the second metal sealing member for providing an enclosure capacitance surrounding the one or more interconnects.