# US 11,114,414 B2 · Wafer structure with capacitive chip interconnection, method for manufacturing the same, and chip structure with capacitive chip interconnection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,114,414 B2 - Document ID: US11114414B2 - Status: Granted - Kind: B2 - Application number: 16/582,620 - Filed: 2019-09-25 - Published: 2021-01-28 - Granted: 2021-09-07 - Earliest claimed: 2019-07-25 - Assignees: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. - Applicants: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. - Inventors: Yang Li; Sheng Hu - Web page: https://patentgrep.com/patent/US11114414B2 ## CPC - H10W 90/00: Package configurations - H10D 1/692: {Electrodes} - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10W 20/42: Vias, e.g. via plugs - H10W 20/43: Layouts of interconnections - H10W 20/496: {Capacitor integral with wiring layers} - H10W 72/00: Interconnections or connectors in packages - H10W 72/0198: {batch processes} - H10W 72/07331: {Connecting techniques} - H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics} - H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 90/293: {characterised by non-galvanic coupling between the chips, e.g. capacitive coupling} - H10W 90/732: {between stacked chips} - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A wafer structure, a method for manufacturing the same and a chip structure are provided. A first capacitor plate is arranged in a first chip, a second capacitor plate is arranged in a second chip, and the first chip is stacked together via bonding layers with the second chip with a front surface of the first chip facing toward a front surface of the second chip. In this way, a capacitor structure formed by the first capacitor plate, the second capacitor plate and dielectric materials provided therebetween is formed while bonding the first chip and second chip together, and the capacitor plate and the dielectric materials may be formed while forming a device interconnection structure in the chip, such that no additional process is required, thereby improving device integration and process integration. ## Claims ### Claim 1 A chip structure, comprising: a first chip, wherein the first chip comprises a first substrate, a first cover layer of a first dielectric material on a front surface of the first substrate, a first capacitor plate and a first plate interconnection structure electrically connected to the first capacitor plate that are arranged in the first cover layer, and a first bonding layer of a second dielectric material on the first cover layer; and a second chip, wherein the second chip comprises a second substrate, a second cover layer of a third dielectric material on a front surface of the second substrate, a second capacitor plate and a second plate interconnection structure electrically connected to the second capacitor plate that are arranged in the second cover layer, and a second bonding layer of a fourth dielectric material on the second cover layer, wherein the first chip is stacked with the second chip via the first bonding layer and the second bonding layer with a front surface of the first chip facing toward a front surface of the second chip, and the first capacitor plate is arranged facing toward the second capacitor plate with at least the second dielectric material and the fourth dielectric material being provided between the first capacitor plate and the second capacitor plate; wherein the first plate interconnection structure comprises an interconnection layer connected to the first capacitor plate; and wherein the first bonding layer is arranged with a bonding pad to lead out the interconnection layer of the first device interconnection structure, and the second bonding layer is arranged with a bonding pad to lead out an interconnection layer of the second device interconnection structure, and wherein the bonding pad of the first bonding layer is aligned with the bonding pad of the second bonding pad. ### Claim 2 (depends on 1) The chip structure according to the claim 1, wherein the first capacitor plate is arranged in a top wiring layer in the first chip, and the second capacitor plate is arranged in a top wiring layer in the second chip. ### Claim 3 (depends on 1) The chip structure according to the claim 1, wherein the first plate interconnection structure comprises a first contact plug on the first substrate, and the first contact plug is connected to the first capacitor plate. ### Claim 4 (depends on 1) The chip structure according to the claim 1, wherein the second plate interconnection structure comprises a second contact plug on the second substrate, and the second contact plug is connected to the second capacitor plate. ### Claim 5 (depends on 1) The chip structure according to the claim 1, wherein the first capacitor plate is arranged in a wiring layer other than a top wiring layer in the first chip, and the second capacitor plate is arranged in a wiring layer other than a top wiring layer in the second chip. ### Claim 6 A wafer structure, comprising a wafer bonding structure, wherein the wafer bonding structure comprises a first wafer and a second wafer that are stacked with each other with a front surface of the first wafer facing toward a front surface of the second wafer, and the wafer bonding structure further comprises a plurality of chip structures arranged in an array, wherein each of the chip structures comprises: a first chip, wherein the first chip comprises a first substrate, a first cover layer of a first dielectric material on a front surface of the first substrate, a first capacitor plate and a first plate interconnection structure electrically connected to the first capacitor plate that are arranged in the first cover layer, and a first bonding layer of a second dielectric material on the first cover layer; and a second chip, wherein the second chip comprises a second substrate, a second cover layer of a third dielectric material on a front surface of the second substrate, a second capacitor plate and a second plate interconnection structure electrically connected to the second capacitor plate that are arranged in the second cover layer, and a second bonding layer of a fourth dielectric material on the second cover layer; wherein the first chip is stacked with the second chip via the first bonding layer and the second bonding layer with a front surface of the first chip facing toward a front surface of the second chip, and the first capacitor plate is arranged facing toward the second capacitor plate with at least the second dielectric material and the fourth dielectric material being provided between the first capacitor plate and the second capacitor plate; wherein the first plate interconnection structure comprises an interconnection layer connected to the first capacitor plate; and wherein the first bonding layer is arranged with a bonding pad to lead out the interconnection layer of the first device interconnection structure, and the second bonding layer is arranged with a bonding pad to lead out an interconnection layer of the second device interconnection structure, and wherein the bonding pad of the first bonding layer is aligned with the bonding pad of the second bonding pad. ### Claim 7 (depends on 6) The wafer structure according to claim 6, wherein the first capacitor plate is arranged in a top wiring layer in the first chip, and the second capacitor plate is arranged in a top wiring layer in the second chip. ### Claim 8 (depends on 6) The wafer structure according to claim 6, wherein the first plate interconnection structure comprises a first contact plug on the first substrate, and the first contact plug is connected to the first capacitor plate. ### Claim 9 (depends on 5) The wafer structure according to claim 5, wherein the second plate interconnection structure comprises a second contact plug on the second substrate, and the second contact plug is connected to the second capacitor plate. ### Claim 10 (depends on 6) The wafer structure according to the claim 6, wherein the first capacitor plate is arranged in a wiring layer other than a top wiring layer in the first chip, and the second capacitor plate is arranged in a wiring layer other than a top wiring layer in the second chip. ### Claim 11 A method for manufacturing a wafer structure, comprising: providing a first wafer, wherein the first wafer is provided with first chips arranged in an array, and each of the first chips comprises a first substrate, a first cover layer of a first dielectric material on a front surface of the first substrate, a first capacitor plate and a first plate interconnection structure electrically connected to the first capacitor plate that are arranged in the first cover layer, and a first bonding layer of a second dielectric material on the first cover layer; providing a second wafer, wherein the second wafer is provided with second chips arranged in an array, and each of the second chips comprises a second substrate, a second cover layer of a third dielectric material on a front surface of the second substrate, a second capacitor plate and a second plate interconnection structure electrically connected to the second capacitor plate that are arranged in the second cover layer, and a second bonding layer of a fourth dielectric material on the second cover layer; and bonding the first wafer and the second wafer together via the first bonding layer and the second bonding layer, to obtain a wafer bonding structure in which the first wafer is stacked with the second wafer with a front surface of the first wafer facing toward a front surface of the second wafer, wherein the first capacitor plate is arranged facing toward the second capacitor plate with at least the second dielectric material and the fourth dielectric material being provided between the first capacitor plate and the second capacitor plate; wherein the first plate interconnection structure comprises an interconnection layer connected to the first capacitor plate; and wherein the first bonding layer is arranged with a bonding pad to lead out the interconnection layer of the first device interconnection structure, and the second bonding layer is arranged with a bonding pad to lead out an interconnection layer of the second device interconnection structure, and wherein the bonding pad of the first bonding layer is aligned with the bonding pad of the second bonding pad. ### Claim 12 (depends on 11) The method for manufacturing a wafer structure according to claim 11, wherein the first capacitor plate is arranged in a top wiring layer in the first chip, and the second capacitor plate is arranged in a top wiring layer in the second chip. ### Claim 13 (depends on 11) The method for manufacturing a wafer structure according to claim 11, further comprising: cutting the wafer bonding structure, to obtain separate chip structures. ### Claim 14 (depends on 11) The method for manufacturing a wafer structure according to claim 11, wherein the first capacitor plate is arranged in a wiring layer other than a top wiring layer in the first chip, and the second capacitor plate is arranged in a wiring layer other than a top wiring layer in the second chip.