# US 11,114,413 B2 · Stacking structure, package structure and method of fabricating the same

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- Number: US 11,114,413 B2
- Document ID: US11114413B2
- Status: Granted
- Kind: B2
- Application number: 16/581,795
- Filed: 2019-09-25
- Published: 2020-12-31
- Granted: 2021-09-07
- Earliest claimed: 2019-06-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Ming-Fa Chen; Sung-Feng Yeh; Tzuan-Horng Liu; Chao-Wen Shih
- Web page: https://patentgrep.com/patent/US11114413B2

## CPC

- H10W 90/00: Package configurations
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/0198: {batch processes}
- H10W 72/90: Bond pads, in general
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 72/01: {Manufacture or treatment}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/07354: {changes in dispositions}
- H10W 72/075: {of bond wires}
- H10W 72/07507: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/07554: {changes in dispositions}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/354: {comprising polymers}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 72/853: {On the same surface}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/701: {characterised by the pads after the direct bonding}
- H10W 80/732: {having shape changed during the connecting}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units.

## Claims

### Claim 1

A package structure, comprising:
a plurality of stacked die units stacked on top of one another, wherein each of the plurality of stacked die units comprises:
a first semiconductor die having a plurality of first bonding pads;
a first bonding chip stacked on the first semiconductor die and having a plurality of first bonding structures, wherein the plurality of first bonding structures is bonded to the plurality of first bonding pads;
a second bonding chip stacked on the first semiconductor die adjacent to the first bonding chip and having a plurality of second bonding structures, wherein the plurality of second bonding structures is bonded to the plurality of first bonding pads, and the second bonding chip is physically separated from the first bonding chip on the first semiconductor die;
an insulating encapsulant encapsulating the plurality of stacked die units and filling into a space between the first bonding chip and the second bonding chip.

### Claim 2 (depends on 1)

The package structure according to claim 1, further comprising a semiconductor substrate, wherein the plurality of stacked die units is attached to the semiconductor substrate through an adhesive layer.

### Claim 3 (depends on 1)

The package structure according to claim 1, further comprising a redistribution layer wherein the plurality of stacked die units is attached to the redistribution layer through an adhesive layer.

### Claim 4 (depends on 1)

The package structure according to claim 1, further comprising a plurality of conductive wires electrically connected to at least one of the first bonding pads in each of the plurality of stacked die units, wherein the insulating encapsulant further encapsulates the conductive wires.

### Claim 5 (depends on 1)

The package structure according to claim 1, wherein at least one of the stacked die units further comprises a second semiconductor die having a plurality of second bonding pads, wherein the first semiconductor die is attached to the second semiconductor die through an adhesive layer.

### Claim 6 (depends on 1)

The package structure according to claim 1, wherein sidewalls of the first semiconductor die in one of the stacked die units is aligned with sidewalls of the first semiconductor die in another one of the stacked die units.

### Claim 7 (depends on 1)

The package structure according to claim 1, wherein the insulating encapsulant covers and is in physical contact with at least one of the plurality of first bonding pads.

### Claim 8

A stacking structure, comprising:
a first stacked die unit, the first stacked die unit comprises:
a first base semiconductor die having bonding pads;
a first controller chip having bonding structures, wherein the first controller chip is stacked on the first base semiconductor die in a way that a first portion of the bonding pads of the first base semiconductor die faces the bonding structures of the first controller chip so that they are physically bonded with one another, while a second portion of the bonding pads of the first base semiconductor die are exposed;
a second stacked die unit stacked on the first stacked die unit, wherein the second stacked die unit comprises:
a second base semiconductor die having bonding pads;
a second controller chip having bonding structures, wherein the second controller chip is stacked on the second base semiconductor die in a way that a first portion of the bonding pads of the second base semiconductor die faces the bonding structures of the second controller chip so that they are physically bonded with one another, while a second portion of the bonding pads of the second base semiconductor die are exposed, and
wherein the second base semiconductor die of the second stacked die unit is attached to the first controller chip of the first stacked die unit, and being spaced apart from the first base semiconductor die by a first distance; and
a bonding wire directly connecting the second portion of the bonding pads of the first base semiconductor die to the second portion of the bonding pads of the second base semiconductor die.

### Claim 9 (depends on 8)

The stacking structure according to claim 8, wherein the second base semiconductor die of the second stacked die unit is attached to the first controller chip of the first stacked die unit through an adhesive layer.

### Claim 10 (depends on 9)

The stacking structure according to claim 9, wherein the first distance is equal to a sum of a thickness of the first controller chip and a thickness of the adhesive layer.

### Claim 11 (depends on 8)

The stacking structure according to claim 8, wherein the first stacked die unit further comprises first auxiliary bonding chips stacked on the first base semiconductor die adjacent to the first controller chip, and the first auxiliary bonding chips have bonding structures that are hybrid bonded to the bonding pads of the first base semiconductor die; and
the second stacked die unit further comprises second auxiliary bonding chips stacked on the second base semiconductor die adjacent to the second controller chip, and the second auxiliary bonding chips have bonding structures that are hybrid bonded to the bonding pads of the second base semiconductor die.

### Claim 12 (depends on 8)

The stacking structure according to claim 8, further comprising an insulating encapsulant encapsulating the first stacked die unit and the second stacked die unit, wherein the insulating encapsulant fills up a space between the first base semiconductor die and the second base semiconductor die defined by the first distance.

### Claim 13

A method of fabricating a package structure, comprising:
forming a plurality of stacked die units by the following steps:
providing a semiconductor wafer having a plurality of first semiconductor dies, wherein each of the plurality of first semiconductor dies has a plurality of first bonding pads;
stacking a plurality of first bonding chips on the semiconductor wafer, wherein each of the plurality of first bonding chips has a plurality of first bonding structures, wherein the plurality of first bonding structures is bonded to the plurality of first bonding pads in a way that two or more of the plurality of first bonding pads are joined with one of the plurality of first bonding structures through hybrid bonding;
dicing the semiconductor wafer to form the plurality of stacked dies units each comprising one of the first bonding chip stacked over one of the first semiconductor die in a build-up direction;
stacking the plurality of stacked dies units on top of one another in the build-up direction; and
forming an insulating encapsulant encapsulating the plurality of stacked die units.

### Claim 14 (depends on 13)

The method of fabricating the package structure according to claim 13, further comprises performing a first thinning step to reduce a thickness of the plurality of first bonding chips.

### Claim 15 (depends on 14)

The method of fabricating the package structure according to claim 14, further comprises performing a second thinning step to reduce a thickness of the plurality of first semiconductor dies.

### Claim 16 (depends on 13)

The method of fabricating the package structure according to claim 13, further comprises:
providing a semiconductor substrate prior to forming the plurality of stacked die units; and
stacking the plurality of stacked die units on the semiconductor substrate using adhesive layers.

### Claim 17 (depends on 13)

The method of fabricating the package structure according to claim 13, further comprises:
providing a carrier and a redistribution layer on the carrier prior to forming the plurality of stacked die units;
stacking the plurality of stacked die units on the redistribution layer using adhesive layers; and
debonding the carrier after forming the insulating encapsulant.

### Claim 18 (depends on 13)

The method of fabricating the package structure according to claim 13, further comprises stacking a plurality of second bonding chips on the semiconductor wafer adjacent to the plurality of first bonding chips, wherein each of the plurality of second bonding chips has a plurality of second bonding structures, and the plurality of second bonding structures is connected to the plurality of first bonding pads through hybrid bonding, and the semiconductor wafer is diced so as to form the plurality of stacked dies units each comprising one of the first bonding chip and one of the second bonding chip stacked over one of the first semiconductor die in the build-up direction.

### Claim 19 (depends on 13)

The method of fabricating the package structure according to claim 13, further comprises attaching a second semiconductor die having a plurality of second bonding pads to at least one of the plurality of first semiconductor dies using an adhesive layer.

### Claim 20 (depends on 13)

The method of fabricating the package structure according to claim 13, further comprises:
providing a plurality of conductive wires electrically connected to at least one of the first bonding pads in each of the plurality of stacked die units; and
forming the insulating encapsulant after providing the plurality of conductive wires.