# US 11,114,412 B2 · Electronic package and method for fabricating the same

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- Number: US 11,114,412 B2
- Document ID: US11114412B2
- Status: Granted
- Kind: B2
- Application number: 16/686,995
- Filed: 2019-11-18
- Published: 2021-04-08
- Granted: 2021-09-07
- Earliest claimed: 2019-10-07
- Assignees: Siliconware Precision Industries Co., Ltd.
- Applicants: Siliconware Precision Industries Co., Ltd.
- Inventors: Hsin-Yi Liao; Cheng-Kai Chang
- Web page: https://patentgrep.com/patent/US11114412B2

## CPC

- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/00: Package configurations
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/072: {of bump connectors}
- H10W 72/075: {of bond wires}
- H10W 74/01: Manufacture or treatment
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/656: Fan-in layouts
- H10W 70/692: Ceramics or glasses
- H10W 70/695: Organic materials
- H10W 72/073: {of die-attach connectors}
- H10W 72/07304: {the auxiliary member being temporary, e.g. a sacrificial coating}
- H10W 72/07504: {the auxiliary member being temporary, e.g. a sacrificial coating}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/30: Die-attach connectors
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/859: {Bump connectors and bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An electronic package is provided, including: a first carrying structure having a first circuit layer; a package module disposed on the first carrying structure and electrically connected to the first circuit layer; a first electronic component disposed on the first carrying structure and electrically connected to the first circuit layer; and a second electronic component stacked on and electrically connected to the first electronic component. As the second electronic component is stacked with the first electronic component, a surface area of the first carrying structure that the first and second electronic components occupy is reduced, and the electronic package can have sufficient space to accommodate the package modules. A method for fabricating an electronic package is also provided.

## Claims

### Claim 1

An electronic package, comprising:
a first carrying structure defined with a first surface and a second surface opposing the first surface and having a first circuit layer;
a package module disposed on the first surface of the first carrying structure and electrically connected to the first circuit layer;
a first electronic component disposed on the first surface of the first carrying structure and electrically connected to the first circuit layer, wherein the first electronic component has a first active surface and a first inactive surface opposing the first active surface, the first inactive surface is adhered to the first surface of the first carrying structure, and a plurality of first electrode pads are disposed on the first active surface; and
a second electronic component stacked on and electrically connected to the first electronic component, wherein the second electronic component has a second active surface and a second inactive surface opposing the second active surface, the second active surface is disposed on the first active surface of the first electronic component, and a plurality of second electrode pads are disposed on the second active surface and electrically connected to the first electrode pads of the first electronic component.

### Claim 2 (depends on 1)

The electronic package of claim 1, wherein the package module comprises:
a second carrying structure having a second circuit layer and disposed on the first surface of the first carrying structure via a plurality of conductors electrically connected to the first circuit layer and the second circuit layer;
at least one functional electronic component disposed on the second carrying structure and electrically connected to the second circuit layer; and
a package layer encapsulating the functional electronic component.

### Claim 3 (depends on 2)

The electronic package of claim 2, wherein the first circuit layer and the second circuit layer have different circuit specification.

### Claim 4 (depends on 2)

The electronic package of claim 2, wherein the first circuit layer has a greater line width/line pitch than the second circuit layer.

### Claim 5 (depends on 1)

The electronic package of claim 1, wherein the first electronic component is electrically connected to the first circuit layer via bonding wires.

### Claim 6 (depends on 1)

The electronic package of claim 1, wherein the second electronic component is electrically connected to the first electronic component via conductive bumps.

### Claim 7 (depends on 1)

The electronic package of claim 1, further comprising an encapsulation layer formed on the first surface of the first carrying structure and encapsulating the first electronic component and the second electronic component.

### Claim 8 (depends on 7)

The electronic package of claim 7, wherein a portion of a surface of the second electronic component is exposed from the encapsulation layer.

### Claim 9 (depends on 7)

The electronic package of claim 7, wherein the encapsulation layer further encapsulates the package module.

### Claim 10 (depends on 1)

The electronic package of claim 1, further comprising a plurality of conductive elements formed on the second surface of the first carrying structure and electrically connected to the first circuit layer.

### Claim 11

A method for fabricating an electronic package, comprising:
providing a first carrying structure having a first circuit layer and defined with a first surface and a second surface opposing the first surface; and
disposing a package module, a first electronic component and a second electronic component on the first surface of the first carrying structure, wherein the package module and the first electronic component are electrically connected to the first circuit layer, and the second electronic component is stacked on and electrically connected to the first electronic component,
wherein the first electronic component has a first active surface and a first inactive surface opposing the first active surface, the first inactive surface is adhered to the first surface of the first carrying structure, and a plurality of first electrode pads are disposed on the first active surface, and
wherein the second electronic component has a second active surface and a second inactive surface opposing the second active surface, the second active surface is disposed on the first active surface of the first electronic component, and a plurality of second electrode pads are disposed on the second active surface and electrically connected to the first electrode pads of the first electronic component.

### Claim 12 (depends on 11)

The method of claim 11, wherein the package module comprises:
a second carrying structure having a second circuit layer and disposed on the first surface of the first carrying structure via a plurality of conductors electrically connected to the first circuit layer and the second circuit layer;
at least one functional electronic component disposed on the second carrying structure and electrically connected to the second circuit layer; and
a package layer encapsulating the functional electronic component.

### Claim 13 (depends on 12)

The method of claim 12, wherein the first circuit layer and the second circuit layer have different circuit specification.

### Claim 14 (depends on 12)

The method of claim 12, wherein the first circuit layer has a greater line width/line pitch than the second circuit layer.

### Claim 15 (depends on 11)

The method of claim 11, wherein the first electronic component is electrically connected to the first circuit layer via bonding wires.

### Claim 16 (depends on 11)

The method of claim 11, wherein the second electronic component is electrically connected to the first electronic component via conductive bumps.

### Claim 17 (depends on 11)

The method of claim 11, further comprising forming an encapsulation layer on the first surface of the first carrying structure, and encapsulating the first electronic component and the second electronic component with the encapsulation layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein a portion of a surface of the second electronic component is exposed from the encapsulation layer.

### Claim 19 (depends on 17)

The method of claim 17, wherein the encapsulation layer further encapsulates the package module.

### Claim 20 (depends on 11)

The method of claim 11, further comprising forming a plurality of conductive elements on the second surface of the first carrying structure and electrically connecting the plurality of conductive elements to the first circuit layer.