# US 11,114,409 B2 · Chip on wafer on substrate optoelectronic assembly and methods of assembly thereof

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- Number: US 11,114,409 B2
- Document ID: US11114409B2
- Status: Granted
- Kind: B2
- Application number: 16/777,569
- Filed: 2020-01-30
- Published: 2021-08-05
- Granted: 2021-09-07
- Earliest claimed: 2020-01-30
- Assignees: Hewlett Packard Enterprise Development LP
- Applicants: Hewlett Packard Enterprise Development LP
- Inventors: Mir Ashkan Seyedi; Marco Fiorentino
- Web page: https://patentgrep.com/patent/US11114409B2

## CPC

- H10W 72/0198: {batch processes}
- H10W 90/00: Package configurations
- H10W 70/095: {of vias therein}
- H10W 70/479: {on or in insulating or insulated package substrates, interposers, or redistribution layers}
- H10W 72/073: {of die-attach connectors}
- H10W 72/30: Die-attach connectors
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- G02B 6/4232: {using the surface tension of fluid solder to align the elements, e.g. solder bump techniques (flip-chip mounting techniques in assembly of semiconductor devices H10W72/072)}
- G02B 6/4255: {Moulded or casted packages}
- G02B 6/4292: {the light guide being disconnectable from the opto-electronic element, e.g. mutually self aligning arrangements}
- H10W 70/635: {Through-vias}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS

## Abstract

Examples herein relate to optoelectronic assemblies. In particular, implementations herein relate to an optoelectronic assembly formed via a chip on wafer on substrate (CoWoS) process. The optoelectronic assembly includes a substrate, an interposer, and an electronic integrated circuit (EIC). Each of the substrate, interposer, and EIC includes opposing first and second sides. The EIC is flip-chip assembled to the first side of the interposer, and the interposer with the EIC assembled thereto is flip-chip assembled to the first side of the substrate. An overmold layer extends over the first side of the interposer and encapsulates the EIC. The overmold layer includes a cavity such that a region of the first side of the interposer is exposed. An optical component is positioned within the cavity and coupled to the first side of the interposer.

## Claims

### Claim 1

A method of assembling an optoelectronic assembly via a CoWos process, the method comprising:
fabricating an interposer with TSVs, the interposer having opposing first and second sides;
flip-chip assembling an electronic integrated circuit (EIC) having opposing first and second sides to the first side of the interposer;
coupling an enclosure to the first side of the interposer, the enclosure having a lid and four sidewalls, and a height greater than a height of the EIC;
depositing an overmold layer on the first side of the interposer, the overmold layer encapsulating the EIC;
planarizing the overmold layer, wherein the lid of the enclosure is removed during planarization of the overmold layer, the four sidewalls of the enclosure forming a cavity extending through the overmold layer and exposing a region of the first side of the interposer;
coupling an optical component to the first side of the interposer within the formed cavity; and
flip-chip assembling the interposer to a first side of a substrate.

### Claim 2 (depends on 1)

The method of assembling an optoelectronic assembly of claim 1, wherein the enclosure is coupled to the first side of the interposer with an adhesive.

### Claim 3 (depends on 1)

The method of assembling an optoelectronic assembly of claim 1, wherein the enclosure is coupled to the first side of the interposer with a solder reflow process.

### Claim 4 (depends on 1)

The method of assembling an optoelectronic assembly of claim 1, wherein the cavity has a rectangular cross-sectional configuration.

### Claim 5 (depends on 1)

The method of assembling an optoelectronic assembly of claim 1, further comprising cleaving one sidewall of the four sidewalls of the enclosure after removing the lid such that the cavity has a U-shaped cross-sectional configuration.

### Claim 6 (depends on 1)

The method of assembling an optoelectronic assembly of claim 1, wherein the enclosure positioned on the first side of the interposer via pick-and-place tools.

### Claim 7 (depends on 1)

The method of assembling an optoelectronic assembly of claim 1, wherein the enclosure and the EIC are coupled to the first side of the interposer simultaneously during a solder reflow process.

### Claim 8 (depends on 1)

The method of assembling an optoelectronic assembly of claim 1, wherein the interposer is flip-chip assembled to the substrate after the planarization of the overmold layer.

### Claim 9 (depends on 1)

The method of assembling an optoelectronic assembly of claim 1, wherein the first and second sides of the EIC and the interposer are top and bottom sides, respectively.

### Claim 10 (depends on 1)

The method of assembling an optoelectronic assembly of claim 1, wherein the TSVs extend from the first side to the second side of the interposer to couple the EIC to the first side of the substrate.