Integrated fan-out package and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Yung-Chi Chu
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Abstract
An integrated fan-out (InFO) package includes an encapsulant, a die, a plurality of conductive structures, and a redistribution structure. The die and the conductive structures are encapsulated by the encapsulant. The conductive structures surround the die. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The conductive vias interconnects the routing patterns. At least one of the alignment mark is in physical contact with the encapsulant.
Claims20
An integrated fan-out (InFO) package having an active region and a border region surrounding the active region, comprising:
- an encapsulant;
- a die and a plurality of conductive structures encapsulated by the encapsulant, wherein the plurality of conductive structures surround the die;
- a redistribution structure disposed on the encapsulant, wherein the redistribution structure comprises a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks, the plurality of conductive vias interconnect the plurality of routing patterns, at least one of the plurality of alignment marks is in physical contact with the encapsulant, the plurality of alignment marks are electrically floating, the plurality of conductive structures and the plurality of alignment marks are located at different level heights, the plurality of alignment marks are located in the border region, each of the plurality of alignment marks is vertically offset from one another in the same border region, and the border region is devoid of the die, the plurality of routing patterns, and the plurality of conductive vias.
An integrated fan-out (InFO) package, comprising:
- an encapsulant;
- a die and a plurality of conductive structures encapsulated by the encapsulant, wherein the plurality of conductive structures surround the die;
- a redistribution structure disposed on the encapsulant, wherein the redistribution structure comprises:
- a first dielectric layer;
- a plurality of first conductive vias embedded in the first dielectric layer;
- a second dielectric layer stacked on the first dielectric layer;
- a plurality of second conductive vias embedded in the second dielectric layer and being free of seed layer;
- a plurality of first routing patterns embedded in the second dielectric layer and being sandwiched between the plurality of first conductive vias and the plurality of second conductive vias;
- a first alignment mark embedded in the first dielectric layer, wherein the first alignment mark comprises a first seed layer and a plurality of first conductive patterns, the plurality of first conductive patterns are stacked on the first seed layer;
- and
- a second alignment mark embedded in the second dielectric layer, wherein the second alignment mark comprises a second seed layer, a second conductive pattern, and a plurality of third conductive patterns, and the second conductive pattern is sandwiched between the second seed layer and the plurality of third conductive patterns.
A manufacturing method of an integrated fan-out (InFO) package having an active region and a border region surrounding the active region, comprising:
- providing a carrier;
- forming a die and a plurality of conductive structures over the carrier, wherein the plurality of conductive structures surround the die;
- encapsulating the die and the plurality of conductive structures by an encapsulant;
- and
- forming a redistribution structure over the encapsulant, wherein the redistribution structure comprises a plurality of routing patterns, a plurality of first conductive vias, a plurality of second conductive vias, a first alignment mark, and a second alignment mark, the plurality of routing patterns is sandwiched between the plurality of the first conducive vias and the plurality of second conductive vias, the first alignment mark is physically in contact with the encapsulant, the first alignment mark and the second alignment mark are electrically floating and are located in the border region, the first alignment mark and the second alignment mark are located at different level heights and are vertically offset from each other in the same border region, and the border region is devoid of the die, the plurality of routing patterns, the plurality of first conductive vias, and the plurality of second conductive vias.
Dependencies are inferred from the claim text.