Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip

A method of forming a semiconductor structure, comprising:

• providing a first semiconductor die including first semiconductor devices, first metal interconnect structures, and first metal bonding pads having first concave top surfaces and embedded in a first pad-level dielectric layer;
• forming metallic bump portions directly on the first concave top surfaces of the first metal bonding pads while a top surface of the first pad-level dielectric layer is physically exposed by selectively depositing a metallic material on the first concave top surfaces of the first metal bonding pads employing a selective metal deposition process while suppressing growth of the metallic material on the physically exposed top surface of the first pad-level dielectric layer;
• providing a second semiconductor die including second semiconductor devices, second metal interconnect structures, and second metal bonding pads;
• and
• attaching the second semiconductor die to the first semiconductor die by bonding the second metal bonding pads to the metallic bump portions via metal-to-metal bonding;
• wherein:
• the metallic bump portions have a greater thickness at a center portion than at an edge portion during the selective metal deposition process;
• the second metal bonding pads have second concave top surfaces;
• and
• the center portions of the metallic bump portions contact the second concave top surfaces of the second metal bonding pads.