# US 11,114,401 B2 · Bonding structure and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,114,401 B2 - Document ID: US11114401B2 - Status: Granted - Kind: B2 - Application number: 16/584,331 - Filed: 2019-09-26 - Published: 2020-11-19 - Granted: 2021-09-07 - Earliest claimed: 2019-05-17 - Assignees: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. - Applicants: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. - Inventors: Fei Liang; Jing Cao; Sheng Hu - Web page: https://patentgrep.com/patent/US11114401B2 ## CPC - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10W 72/90: Bond pads, in general - H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices - H10W 72/30: Die-attach connectors - H10W 90/00: Package configurations - H10W 72/01951: {Changing the shapes of bond pads} - H10W 72/0198: {batch processes} - H10W 72/073: {of die-attach connectors} - H10W 72/07331: {Connecting techniques} - H10W 72/07354: {changes in dispositions} - H10W 72/347: {Dispositions of multiple die-attach connectors} - H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics} - H10W 72/834: {Interconnections on sidewalls of chips} - H10W 72/851: {Dispositions of multiple connectors or interconnections} - H10W 72/941: {Dispositions of bond pads} - H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A bonding structure and a method for manufacturing the bonding structure are provided. Multiple chips arranged in an array are formed on a surface of a wafer. Each of the chips includes a device structure, an interconnect structure electrically connected to the device structure, and a first package pad layer electrically connected to the interconnect structure. The first package pad layer is arranged at an edge region of the chip. A chip stack is obtained after bonding and cutting the multiple wafers, and the first package pad layer at the edge region of the chip is exposed. ## Claims ### Claim 1 A method for manufacturing a bonding structure, comprising: providing a plurality of wafers, wherein each of the plurality of wafers has a first surface and a second surface opposite to the first surface; a plurality of chips arranged in an array is formed on the first surface, and each of the plurality of chips comprises a device structure, an interconnect structure electrically connected to the device structure, and a first package pad layer electrically connected to the interconnect structure; and the first package pad layer is arranged at an edge region of the chip; bonding the plurality of wafers via bonding layers, to form a wafer stack; cutting the wafer stack along a scribe line located among the plurality of chips to obtain a chip stack; exposing the first package pad layer at the edge region of each chip in the chip stack; providing a package substrate, wherein the package substrate is provided with electrical connections and a second package pad layer electrically connected to the electrical connections; and electrically connecting the first package pad layer of each chip in the chip stack to the second package pad layer of the package substrate. ### Claim 2 (depends on 1) The method according to claim 1, wherein bonding the plurality of wafers via the bonding layers comprises: for two adjacent wafers in the wafer stack, bonding the first surface of one wafer to the first surface of the other wafer via one of the bonding layers; or bonding the first surface of one wafer to the second surface of the other wafer via one of the bonding layers. ### Claim 3 (depends on 2) The method according to claim 2, wherein bonding the plurality of wafers via the bonding layers comprises: performing thinning from the second surface of one of the plurality of wafers; and bonding the one of the plurality of wafers to another of the plurality of wafers, before or after the thinning. ### Claim 4 (depends on 1) The method according to claim 1, wherein bonding the plurality of wafers via the bonding layers comprises: for two adjacent wafers in the wafer stack, bonding the second surface of one wafer to the second surface of the other wafer via one of the bonding layers. ### Claim 5 (depends on 4) The method according to claim 4, wherein bonding the plurality of wafers via the bonding layers further comprises: thinning the two adjacent wafers from the second surfaces. ### Claim 6 (depends on 3) The method according to claim 3, wherein thinning comprises: performing thinning from the second surface of the one of the plurality of wafers by an acid etching; performing thinning from the second surface of the one of the plurality of wafers by a chemical mechanical polishing; or performing etching from the second surface of the one of the plurality of wafers by an acid etching, and then planarizing the second surface of the one of the plurality of wafers by a chemical mechanical polishing. ### Claim 7 (depends on 1) The method according to claim 1, wherein the exposing the first package pad layer at the edge region of each chip in the chip stack comprises: polishing a side of the chip stack to expose the first package pad layer at the edge region of each chip in the chip stack. ### Claim 8 (depends on 5) The method according to claim 5, wherein the thinning comprises: performing thinning from the second surfaces of the two adjacent wafers by an acid etching; performing thinning from the second surfaces of the two adjacent wafers by a chemical mechanical polishing; or performing etching from the second surfaces of the two adjacent wafers by an acid etching, and then planarizing the second surfaces of the two adjacent wafers by a chemical mechanical polishing. ### Claim 9 A bonding structure, comprising: a chip stack formed by laminating chips in sequence, wherein a bonding layer is arranged between every two adjacent ones of the chips, and each chip comprises: a device structure, an interconnect structure electrically connected to the device structure, and a first package pad layer electrically connected to the interconnect structure, wherein the first package pad layer is arranged at an edge region of said chip; and a package substrate, provided with electrical connections and a second package pad layer electrically connected to the electrical connections, wherein the first package pad layer of each chip in the chip stack is electrically connected to the second package pad layer of the package substrate. ### Claim 10 (depends on 9) The bonding structure according to claim 9, wherein the device structures of the chips of the chip stack are different. ### Claim 11 (depends on 9) The bonding structure according to claim 9, wherein a quantity of the chips is three or more. ### Claim 12 (depends on 9) The bonding structure according to claim 9, wherein no via hole is provided in the bonding structure to electrically connect different ones of the chips.