# US 11,114,400 B2 · Semiconductor device with improved thermal dissipation and manufacturing methods

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- Number: US 11,114,400 B2
- Document ID: US11114400B2
- Status: Granted
- Kind: B2
- Application number: 16/123,377
- Filed: 2018-09-06
- Published: 2020-03-12
- Granted: 2021-09-07
- Earliest claimed: 2018-09-06
- Assignees: Amkor Technology Singapore Holding Pte.Ltd.
- Applicants: Amkor Technology Singapore Holding Pte. Ltd.
- Inventors: Cameron Nelson
- Web page: https://patentgrep.com/patent/US11114400B2

## CPC

- H10W 40/10: Arrangements for heating
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 74/47: comprising organic materials, e.g. plastics or resins
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/652: Cross-sectional shapes
- H10W 70/655: Fan-out layouts
- H10W 70/656: Fan-in layouts
- H10W 70/66: Conductive materials thereof
- H10W 70/69: Insulating materials thereof
- H10W 72/019: {of bond pads}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/90: Bond pads, in general
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/965: {Providing thermal transfer}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 72/981: {Auxiliary members, e.g. spacers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor die, a redistribution structure, a interconnection structure, and a thermal path structure. The redistribution structure includes an insulation layer over a first surface of the semiconductor die and a conductive trace separated from the first surface by the insulation layer. The conductive trace extends laterally over the first surface from a first end toward a second end that is electrically coupled to a bond pad on the first surface of the semiconductor die. The interconnection structure is coupled to the first end of the conductive trace. The thermal path structure provides a thermal path between the semiconductor die and the interconnection structure. In some embodiment, the thermal path structure comprises a thermal pad that passes through the insulation layer. In other embodiments, the thermal path structure comprises a dummy pad on the first surface of the semiconductor die.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor die comprising a die top side and a die bottom side;
a circuit integrated in the semiconductor die;
a bond pad comprising a bond pad top side and bond pad bottom side, wherein the bond pad top side is on the die bottom side, and wherein the bond pad is electrically coupled to the circuit via the bond pad top side;
a dummy pad comprising a dummy pad top side and dummy pad bottom side, wherein the dummy pad top side is on the die bottom side, and wherein the dummy pad is not electrically coupled to the circuit via the dummy pad top side;
a redistribution structure comprising an insulation layer over the die bottom side and a conductive trace separated from the die bottom side by the insulation layer, wherein the conductive trace extends laterally over the die bottom side from a first conductive trace portion coupled to the dummy pad toward a second conductive trace portion coupled to the bond pad; and
an interconnection structure coupled to the first conductive trace portion;
wherein the dummy pad provides a first thermal path that follows a straight line from the die bottom side through the dummy pad to the interconnection structures;
wherein the bond pad and the conductive trace provide a second thermal path between the semiconductor die and the interconnection structure; and
wherein the first thermal path provides greater thermal conductivity between the semiconductor die and the interconnection structure than the second thermal path provides.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the dummy pad is in direct contact with the die bottom side.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein:
the redistribution structure comprises a second insulation layer on the conductive trace and the insulation layer; and
the interconnection structure comprises a solder ball attached to the first conductive trace portion via an opening in the second insulation layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein:
the semiconductor die further comprises a passivation layer; and
the passivation layer defines at least a portion of the die bottom side.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the passivation layer comprises a bond pad opening through which the bond pad is coupled to the second conductive trace portion and a dummy pad opening through which the dummy pad is coupled to the first conductive trace portion.

### Claim 6

A method of fabricating a semiconductor device, comprising:
providing a semiconductor die, a circuit integrated in the semiconductor die, and a bond pad, wherein the semiconductor die comprises a die top side and a die bottom side, wherein the bond pad comprising a bond pad top side and a bond pad bottom side, wherein the bond pad top side is on the die bottom side, and wherein the bond pad is electrically coupled to the circuit via the bond pad top side;
forming a single insulation layer of a redistribution structure on the die bottom side such that a top side of the single insulation layer contacts the die bottom side;
providing a thermal path structure comprising a thermal path structure top side and a thermal path structure bottom side, wherein the thermal path structure top side is coupled to the die bottom side;
forming a conductive trace of the redistribution structure on the single insulation layer such that the conductive trace is separated from the die bottom side by the single insulation layer, a top side of the conductive trace contacts a bottom side of the single insulation layer, the conductive trace extends laterally over the die bottom side from a first conductive trace portion toward a second conductive trace portion, a top side of the first conductive trace portion is coupled to the thermal path structure bottom side, and a top side of the second conductive trace portion is coupled to the bond pad; and
coupling an interconnection structure to a bottom side of the first conductive trace portion.

### Claim 7 (depends on 6)

The method of claim 6, wherein forming the thermal path structure comprises forming a thermal pad that has a greater thermal conductivity than the single insulation layer.

### Claim 8 (depends on 6)

The method of claim 6, wherein forming the thermal path structure comprises forming a dummy pad structure such that a dummy pad top side is on the die bottom side and the dummy pad is not electrically coupled to the circuit via the dummy pad top side.

### Claim 9

A semiconductor device, comprising:
a semiconductor die comprising a die top side and a die bottom side;
a circuit integrated in the semiconductor die;
a bond pad comprising a bond pad top side and a bond pad bottom side, wherein the bond pad top side is on the die bottom side, and wherein the bond pad is electrically coupled to the circuit via the bond pad top side;
a redistribution structure comprising an insulation layer over the die bottom side and a conductive trace separated from the die bottom side by the insulation layer, wherein the insulation layer comprises an insulation layer top side and an insulation layer bottom side, wherein the insulation layer top side contacts the die bottom side and the insulation layer bottom side contacts a top side of the conductive trace, wherein the conductive trace extends laterally over the die bottom side from a first conductive trace portion toward a second conductive trace portion, and wherein a top side of the second conductive trace portion is coupled to the bond pad;
a thermal path structure between the first conductive trace portion and the die bottom side, wherein the thermal path structure comprises a thermal path structure top side and a thermal path structure bottom side, the thermal path structure top side is coupled to the die bottom side, and the thermal path structure bottom side is coupled to a top side of the first conductive trace portion; and
an interconnection structure coupled to a bottom side of the first conductive trace portion.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein:
the thermal path structure comprises a thermal pad that passes through the insulation layer; and
the thermal pad has a higher thermal conductivity than the insulation layer.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the thermal path structure comprises a dielectric material having a higher thermal conductivity than the insulation layer.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein:
the semiconductor die further comprises a passivation layer;
the passivation layer defines at least a portion of the die bottom side; and
the thermal path structure is in direct contact with the die bottom side.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the insulation top side contacts the passivation layer of the die bottom side.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein:
the semiconductor die further comprises a passivation layer;
the passivation layer defines at least a portion of the die bottom side; and
the passivation layer comprises an opening through which the bond pad is coupled to the second conductive trace portion.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein:
the thermal path structure comprises a thermal pad that passes through the insulation layer;
the thermal pad comprises a pad top side and a pad bottom side;
the pad bottom side is in direct contact with the first conductive trace portion; and
the pad top side is in direct contact with the passivation layer.

### Claim 16 (depends on 9)

The semiconductor device of claim 9, wherein:
the redistribution structure comprises a second insulation layer on the conductive trace and the insulation layer; and
the interconnection structure comprises a solder ball coupled to the first conductive trace portion via an opening in the second insulation layer.

### Claim 17 (depends on 9)

The semiconductor device of claim 9, wherein:
the thermal path structure comprises a dummy pad;
the dummy pad comprises a dummy pad top side on the die bottom side;
the dummy pad is not electrically coupled to the circuit via the bond pad top side; and
the dummy pad is in direct contact with the die bottom side.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein:
the semiconductor die further comprises a passivation layer;
the passivation layer defines at least a portion of the die bottom side; and
the passivation layer comprises a bond pad opening through which the bond pad is coupled to the second conductive trace portion and a dummy pad opening through which the dummy pad is coupled to the first conductive trace portion.

### Claim 19 (depends on 9)

The semiconductor device of claim 9, wherein:
the thermal path structure and the conductive trace provide a thermal path from the die bottom side to the interconnection structure; and
the thermal path provides an all metallic path along a single, straight line from the die bottom side to the interconnection structure.

### Claim 20

A semiconductor device, comprising:
a semiconductor die comprising a die top side and a die bottom side;
a circuit integrated in the semiconductor die;
a bond pad comprising a bond pad top side and a bond pad bottom side, wherein the bond pad top side is on the die bottom side, and wherein the bond pad is electrically coupled to the circuit via the bond pad top side;
a redistribution structure comprising an insulation layer over the die bottom side and a conductive trace separated from the die bottom side by the insulation layer, wherein the insulation layer comprises an insulation layer top side and an insulation layer bottom side, wherein the insulation layer top side contacts the die bottom side and the insulation layer bottom side contacts a top side of the conductive trace, wherein the conductive trace extends laterally over the die bottom side from a first conductive trace portion toward a second conductive trace portion, and wherein a top side of the second conductive trace portion is coupled to the bond pad;
a thermal path structure between the first conductive trace portion and the die bottom side, wherein the thermal path structure comprises a thermal path structure top side and a thermal path structure bottom side, the thermal path structure top side is coupled to the die bottom side, and the thermal path structure bottom side is coupled to a top side of the first conductive trace portion; and
an interconnection structure coupled to a bottom side of the first conductive trace portion, wherein:
the thermal path structure and the conductive trace provide a first thermal path from the die bottom side to the interconnection structure;
the bond pad and the conductive trace provide a second thermal path between the semiconductor die and the interconnection structure; and
the first thermal path provides greater thermal conductivity between the semiconductor die and the interconnection structure than the second thermal path provides.

### Claim 21 (depends on 20)

The semiconductor device of claim 20, wherein:
the semiconductor die further comprises a passivation layer;
the passivation layer defines at least a portion of the die bottom side; and
the thermal path structure is in direct contact with the die bottom side.

### Claim 22 (depends on 20)

The semiconductor device of claim 20, wherein:
the redistribution structure comprises a second insulation layer on the conductive trace and the insulation layer; and
the interconnection structure comprises a solder ball coupled to the first conductive trace portion via an opening in the second insulation layer.

### Claim 23 (depends on 20)

The semiconductor device of claim 20, wherein:
the thermal path structure comprises a dummy pad;
the dummy pad comprises a dummy pad top side on the die bottom side;
the dummy pad is not electrically coupled to the circuit via the bond pad top side; and
the dummy pad is in direct contact with the die bottom side.