# US 11,114,399 B2 · Semiconductor wafer with void suppression and method for producing same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,114,399 B2
- Document ID: US11114399B2
- Status: Granted
- Kind: B2
- Application number: 16/955,448
- Filed: 2018-10-25
- Published: 2020-11-05
- Granted: 2021-09-07
- Earliest claimed: 2017-12-19
- Assignees: JX Nippon Mining & Metals Corporation
- Applicants: Jx Nippon Mining & Metals Corporation
- Inventors: Takuto Watanabe; Katsuyuki Tsuchida
- Web page: https://patentgrep.com/patent/US11114399B2

## CPC

- C23C 18/1651: {Two or more layers only obtained by electroless plating}
- C23C 18/32: Coating with nickel, cobalt or mixtures thereof with phosphorus or boron (C23C18/50 takes precedence)
- C23C 18/1635: {Composition of the substrate}
- C23C 18/1642: {semiconductor (semiconductor H10P14/48)}
- C23C 18/36: using hypophosphites
- C23C 18/44: using reducing agents
- C23C 18/54: Contact plating, i.e. electroless electrochemical plating
- C23C 18/1893: {with use of organic or inorganic compounds other than metals, first}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/90: Bond pads, in general
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor wafer suppressed in voids produced in the interface between a passivation film and an electroless nickel plating film, and configured such that an electrode pad is entirely covered by the electroless nickel plating film. The semiconductor wafer includes, on a substrate, an electrode pad and a passivation film covering the upper surface of the substrate and an opening from which the electrode pad is exposed. The semiconductor wafer sequentially includes, on the electrode pad, an electroless nickel plating film, an electroless palladium plating film and an electroless gold plating film. A void, present in the interface between the passivation film and the electroless nickel plating film, has a length from the forefront of the void to the surface of the electrode pad of 0.3 μm or more and a width of 0.2 μm or less. The electrode pad is entirely covered by the electroless nickel plating film.

## Claims

### Claim 1

A semiconductor wafer, including:
a substrate provided thereon with
an electrode pad;
a passivation film that covers the upper surface of the substrate and has an opening for exposing the electrode pad; and
an electrolessly-plated nickel film formed on the electrode pad, an electrolessly-plated palladium film formed on the electrolessly-plated nickel film, and an electrolessly-plated gold film formed on the electrolessly-plated palladium film,
wherein a void exists at an interface between the passivation film and the electrolessly-plated nickel film, the void having a length from a tip of the void to the surface of the electrode pad of 0.3 μm or more and a width of 0.2 μm or less, and the entire surface of the electrode pad is covered with the electrolessly-plated nickel film.

### Claim 2 (depends on 1)

The semiconductor wafer according to claim 1, wherein the electrolessly-plated nickel film, the electrolessly-plated palladium film, and the electrolessly-plated gold film have a film thickness of 0.5 μm to 15.0 μm, 0.02 μm to 0.50 μm, and 0.01 μm to 0.50 μm, respectively.

### Claim 3 (depends on 1)

The semiconductor wafer according to claim 1, wherein the electrolessly-plated gold film includes a displacement gold plated film and a reduction gold plated film, the displacement gold plated film has a thickness of 0.01 μm or less, and the reduction gold plated film has a thickness of 0.01 μm or more.

### Claim 4 (depends on 1)

A method for producing the semiconductor wafer according to claim 1, the method including the steps of:
forming the electrode pad on the substrate;
forming the passivation film on the upper surface of the substrate on which the electrode pad is formed;
forming the opening that exposes the electrode pad in the passivation film;
forming, on the exposed electrode pad, the electrolessly-plated nickel film, forming the electrolessly-plated palladium film, and forming the electrolessly-plated gold film,
wherein forming the electrolessly-plated gold film includes forming an electrolessly-plated displacement gold film and forming an electrolessly-plated reduction gold film, and
in forming the electrolessly-plated displacement gold film, electroless displacement gold plating is performed on the palladium plated film by using, as the electroless displacement gold plating liquid, an electroless displacement gold plating liquid that provides a plated film with a thickness of 20 nm or less upon plating at a plating temperature of 80° C. and a plating time of 15 minutes, or electroless displacement gold plating is performed under plating conditions that provide a plated film with a thickness of 20 nm or less when an electroless displacement gold plating liquid that provides a plated film with a thickness of above 20 nm upon plating at a plating temperature of 80° C. and a plating time of 15 minutes is used.