# US 11,114,397 B2 · Semiconductor package substrate and method of manufacturing semiconductor package using the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,114,397 B2 - Document ID: US11114397B2 - Status: Granted - Kind: B2 - Application number: 16/663,735 - Filed: 2019-10-25 - Published: 2020-10-01 - Granted: 2021-09-07 - Earliest claimed: 2019-03-28 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Tae Ho Ko; Dae Hee Lee; Hyun Chul Jung; Myeong Ho Hong - Web page: https://patentgrep.com/patent/US11114397B2 ## CPC - H10P 72/74: {using temporarily an auxiliary support} - H10W 72/90: Bond pads, in general - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/479: {on or in insulating or insulated package substrates, interposers, or redistribution layers} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/687: {characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage} - H10W 70/69: Insulating materials thereof - H10W 72/019: {of bond pads} - H10W 72/071: {Connecting or disconnecting} - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)} - H10W 74/147: {the encapsulations being multilayered} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10P 72/7438: {with parts of the auxiliary support remaining in the finished device} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/341: {Dispositions of die-attach connectors, e.g. layouts} - H10W 72/9413: {on encapsulations} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 90/00: Package configurations - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Provided in a semiconductor package substrate including a semiconductor chip including a connection pad, an encapsulant encapsulating at least a portion of the semiconductor chip, a connection member disposed on the semiconductor chip and the encapsulant, the connection member including a redistribution layer that is electrically connected to the connection pad, a first passivation layer disposed on the connection member, and an adhesive layer disposed on at least one of a top surface of the encapsulant and a bottom surface of the first passivation layer in a region outside of the semiconductor chip. ## Claims ### Claim 1 A semiconductor package substrate comprising: a semiconductor chip comprising a connection pad; an encapsulant encapsulating at least a portion of the semiconductor chip; a connection member disposed on the semiconductor chip and a bottom surface of the encapsulant, the connection member comprising a redistribution layer that is electrically connected to the connection pad; a first passivation layer disposed on the connection member; and an adhesive layer disposed on a top surface of the encapsulant in a region outside of the semiconductor chip. ### Claim 2 (depends on 1) The semiconductor package substrate of claim 1, wherein the semiconductor package substrate comprises a first region and a second region, wherein the semiconductor chip is disposed in the first region, and the second region is a dummy region, and wherein the adhesive layer is disposed in the second region. ### Claim 3 (depends on 2) The semiconductor package substrate of claim 2, wherein the second region has a shape of at least one square ring surrounding the first region, and wherein the adhesive layer is disposed in the second region and has a rectangular ring shape. ### Claim 4 (depends on 1) The semiconductor package substrate of claim 1, wherein the adhesive layer is a no flow resin (NFR) layer. ### Claim 5 (depends on 1) The semiconductor package substrate of claim 1, further comprising: a second passivation layer covering the adhesive layer that is disposed on the top surface of the encapsulant. ### Claim 6 (depends on 1) The semiconductor package substrate of claim 1, further comprising: a backside redistribution layer disposed on a second surface of the semiconductor chip opposing a first surface of the semiconductor chip on which the connection member is disposed, the backside redistribution layer being electrically connected to the connection pad, wherein the adhesive layer is disposed parallel to the backside redistribution layer on the top surface of the encapsulant. ### Claim 7 (depends on 1) The semiconductor package substrate of claim 1, further comprising: an underbump metal layer disposed on the connection member, wherein the adhesive layer is disposed parallel to the underbump metal layer on the bottom surface of the first passivation layer. ### Claim 8 (depends on 1) The semiconductor package substrate of claim 1, further comprising: a frame comprising a through-portion, wherein the semiconductor chip is disposed in the through-portion, and the encapsulant fills at least a portion of the through-portion. ### Claim 9 (depends on 2) The semiconductor package substrate of claim 2, wherein the adhesive layer is disposed on the top surface of the encapsulant and the bottom surface of the first passivation layer. ### Claim 10 (depends on 7) The semiconductor package substrate of claim 7, further comprising an electrical connection metal disposed on the underbump metal layer, wherein a portion of the electrical connection metal is disposed in the region outside of the semiconductor chip. ### Claim 11 (depends on 6) The semiconductor package substrate of claim 6, further comprising: a second passivation layer covering the adhesive layer that is disposed on the top surface of the encapsulant and a portion of the backside redistribution layer. ### Claim 12 (depends on 1) The semiconductor package substrate of claim 1, wherein the adhesive layer is disposed so as not to overlap with the semiconductor chip in a vertical direction. ### Claim 13 (depends on 1) The semiconductor package substrate of claim 1, wherein the adhesive layer includes an epoxy-based resin. ### Claim 14 A semiconductor package substrate comprising: a semiconductor chip comprising a connection pad; an encapsulant encapsulating at least a portion of the semiconductor chip; a connection member disposed on the semiconductor chip and the encapsulant, the connection member comprising a redistribution layer that is electrically connected to the connection pad; a first passivation layer disposed on the connection member; and an adhesive layer disposed on at least one of a top surface of the encapsulant and a bottom surface of the first passivation layer in a region outside of the semiconductor chip; a frame comprising a through-portion, the semiconductor chip being disposed in the through-portion, and the encapsulant filling at least a portion of the through-portion, wherein the frame comprises: a first insulating layer disposed in contact with a first surface of the connection member a first wiring layer disposed in contact with the first surface of the connection member and embedded in the first insulating layer, a second wiring layer disposed on a side of the first insulating layer opposing a side in which the first wiring layer is embedded, a second insulating layer disposed on the side of the first insulating layer opposing the side in which the first wiring layer is embedded, the second insulating layer covering at least a portion of the second wiring layer, and a third wiring layer disposed on a side of the second insulating layer opposing a side in which the second wiring layer is embedded, and wherein a surface of the first insulating layer, disposed in contact with the first surface of the connection member, has a step structure with respect to a surface of the first wiring layer disposed in contact with the first surface of the connection member. ### Claim 15 (depends on 14) The semiconductor package substrate of claim 14, wherein the frame further comprises: a first wiring via layer disposed between the first wiring layer and the second wiring layer; and a second wiring via layer disposed between the second wiring layer and the third wiring layer, and wherein each of the first wiring via layer and the second wiring via layer have a tapered shape. ### Claim 16 (depends on 14) The semiconductor package substrate of claim 14, wherein the adhesive layer is disposed so as not to overlap with the semiconductor chip in a vertical direction. ### Claim 17 A semiconductor package substrate comprising: a semiconductor chip comprising a connection pad; an encapsulant encapsulating at least a portion of the semiconductor chip; a connection member disposed on the semiconductor chip and the encapsulant, the connection member comprising a redistribution layer that is electrically connected to the connection pad; a first passivation layer disposed on the connection member; and an adhesive layer disposed on at least one of a top surface of the encapsulant and a bottom surface of the first passivation layer in a region outside of the semiconductor chip; a frame comprising a through-portion, the semiconductor chip being disposed in the through-portion, and the encapsulant filling at least a portion of the through-portion, wherein the frame comprises: a first insulating layer, a first wiring layer and a second wiring layer respectively disposed on opposing surfaces of the first insulating layer, a second insulating layer and a third insulating layer respectively disposed on the opposing surfaces of the first insulating layer, and respectively covering at least a portion of the first wiring layer and at least a portion of the second wiring layer, a third wiring layer disposed on a side of the second insulating layer opposing a side in which the first wiring layer is embedded, and a fourth wiring layer disposed on a side of the third insulating layer opposing a side in which the second wiring layer is embedded, and wherein a thickness of the first insulating layer is greater than a thickness of each of the second insulating layer and the third insulating layer. ### Claim 18 (depends on 17) The semiconductor package substrate of claim 17, wherein the adhesive layer is disposed so as not to overlap with the semiconductor chip in a vertical direction.