Substrate structure and method for manufacturing a semiconductor package
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorShun Sing Liao
Life of this patent
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Abstract
A substrate structure includes a chip attach area and an upper side rail surrounding the chip attach area. The upper side rail includes an upper stress relief structure and an upper reinforcing structure. The upper stress relief structure surrounds the upper chip attach area. The upper reinforcing structure surrounds the upper stress relief structure. A stress relieving ability of the upper stress relief structure is greater than a stress relieving ability of the upper reinforcing structure. A structural strength of the upper reinforcing structure is greater than a structural strength of the upper stress relief structure.
Claims16
A method for manufacturing a semiconductor package, comprising:
- (a) providing a substrate structure, wherein the substrate structure includes a chip attach area and an upper side rail surrounding the chip attach area, the upper side rail includes an upper stress relief structure and an upper reinforcing structure, the upper stress relief structure surrounds the upper chip attach area, the upper reinforcing structure surrounds the upper stress relief structure, wherein a stress relieving ability of the upper stress relief structure is greater than a stress relieving ability of the upper reinforcing structure, and a structural strength of the upper reinforcing structure is greater than a structural strength of the upper stress relief structure, wherein the upper stress relief structure includes copper, the upper reinforcing structure includes copper, and a residual copper ratio of the upper reinforcing structure is greater than a residual copper ratio of the upper stress relief structure;
- (b) attaching at least one semiconductor chip to the chip attach area;
- and
- (c) forming an encapsulant to cover the at least one semiconductor chip.
A method for manufacturing a semiconductor package, comprising:
- (a) providing a substrate structure, wherein the substrate structure includes a chip attach area and an upper side rail surrounding the chip attach area, the upper side rail includes an upper stress relief structure and an upper reinforcing structure, the upper stress relief structure surrounds the upper chip attach area, the upper reinforcing structure surrounds the upper stress relief structure, wherein a stress relieving ability of the upper stress relief structure is greater than a stress relieving ability of the upper reinforcing structure, and a structural strength of the upper reinforcing structure is greater than a structural strength of the upper stress relief structure, wherein the upper stress relief structure has at least two stress relief directions, and the stress relief directions are neither perpendicular to nor parallel with an edge of the substrate structure;
- (b) attaching at least one semiconductor chip to the chip attach area;
- and
- (c) forming an encapsulant to cover the at least one semiconductor chip.
Dependencies are inferred from the claim text.