# US 11,114,381 B2 · Power distribution network for 3D logic and memory

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- Number: US 11,114,381 B2
- Document ID: US11114381B2
- Status: Granted
- Kind: B2
- Application number: 16/560,544
- Filed: 2019-09-04
- Published: 2020-03-05
- Granted: 2021-09-07
- Earliest claimed: 2018-09-05
- Assignees: Tokyo Electron Limited
- Applicants: Tokyo Electron Limited
- Inventors: Lars Liebmann; Jeffrey Smith; Anton J. deVilliers; Kandabara Tapily
- Web page: https://patentgrep.com/patent/US11114381B2

## CPC

- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 20/427: {Power or ground buses}
- H10B 10/12: {comprising a MOSFET load element}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 88/01: {Manufacture or treatment}
- H10D 89/105: {adapted for thermal considerations}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 90/00: Package configurations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device is provided. The semiconductor device includes a transistor stack having a plurality of transistor pairs that are stacked over a substrate. Each transistor pair of the plurality of transistor pairs includes a n-type transistor and a p-type transistor that are stacked over one another. The plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs. The semiconductor device further includes one or more conductive planes formed over the substrate. The one or more conductive planes are positioned adjacent to the transistor stack, span a height of the transistor stack and are electrically coupled to the transistor stack.

## Claims

### Claim 1

A semiconductor device, comprising:
a transistor stack having a plurality of transistor pairs that are stacked over a substrate, wherein each transistor pair of the plurality of transistor pairs includes a n-type transistor and a p-type transistor that are stacked over one another, the plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs; and
one or more conductive planes formed over the substrate, the one or more conductive planes being positioned adjacent to the transistor stack, spanning a height of the transistor stack and being electrically coupled to the transistor stack.

### Claim 2 (depends on 1)

The device of claim 1, further comprising:
a plurality of power rails that are positioned below the transistor stack, wherein each of the one or more conductive planes is positioned over and extends along a respective power rail of the plurality of power rails so as to form a continuous connection.

### Claim 3 (depends on 1)

The device of claim 1, further comprising:
a plurality of power rails that are positioned below the transistor stack, wherein each of the one or more conductive planes is positioned over and across two or more power rails of the plurality of power rails so as to form two or more connection points.

### Claim 4 (depends on 2)

The device of claim 2, wherein the one or more conductive planes comprise a continuous lateral structure to draw power from the plurality of power rails into the transistor stack.

### Claim 5 (depends on 2)

The device of claim 2, wherein the one or more conductive planes comprise a piecewise interrupted structure with one or more channels being arranged therein, the piecewise interrupted structure being configured to create a conductive path from the plurality of power rails into the transistor stack.

### Claim 6 (depends on 1)

The device of claim 1, further comprising:
a plurality of power rails, the plurality of power rails being positioned over the one or more conductive planes, each of the one or more conductive planes being positioned along a respective power rail of the plurality of power rails so as to form a continuous connection.

### Claim 7 (depends on 1)

The device of claim 1, wherein one or more of the plurality of S/D local interconnects are electrically coupled to the one or more conductive planes.

### Claim 8 (depends on 1)

The device of claim 1, further comprising:
a plurality of vertical contacts formed in a direction perpendicular to the substrate and electrically coupled to the plurality of S/D local interconnects, at least one of the plurality of vertical contacts being electrically coupled to an output signal.

### Claim 9 (depends on 1)

The device of claim 1, wherein the n-type transistor and the p-type transistor share a gate structure that is electrically coupled to one of the plurality of gate electrodes.

### Claim 10

A method of forming a semiconductor device, comprising:
forming a transistor stack including a plurality of transistor pairs that are stacked over a substrate, wherein each transistor pair of the plurality of transistor pairs includes a n-type transistor and a p-type transistor that are stacked over one another, the plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs; and
forming one or more conductive planes over the substrate, the one or more conductive planes being positioned adjacent to the transistor stack, spanning a height of the transistor stack and being electrically coupled to the transistor stack.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming a plurality of power rails, the plurality of power rails being positioned below the transistor stack, each of the one or more conductive planes extending along a respective power rail of the plurality of power rails so as to form a continuous connection.

### Claim 12 (depends on 10)

The method of claim 10, further comprising:
forming a plurality of power rails, the plurality of power rails being positioned below the transistor stack, each of the one or more conductive planes being positioned over and across two or more power rails of the plurality of power rails so as to form two or more connection points.

### Claim 13 (depends on 10)

The method of claim 10, further comprising:
forming a plurality of power rails, the plurality of power rails being positioned over the one or more conductive planes, each of the plurality of power rails extending along a respective power rail of the plurality of power rails so as to form a continuous connection.

### Claim 14 (depends on 10)

The method of claim 10, wherein the one or more conductive planes comprises a continuous lateral structure to draw power from a plurality of power rails into the transistor stack.

### Claim 15 (depends on 10)

The method of claim 10, wherein the one or more conductive planes comprises a piecewise interrupted structure that leaves channels and draws power from a plurality of power rails into the transistor stack.

### Claim 16 (depends on 10)

The method of claim 10, wherein one or more of the plurality of S/D local interconnects are electrically coupled to the one or more conductive planes.

### Claim 17 (depends on 10)

The method of claim 10, further comprising:
forming a plurality of vertical contacts that are positioned in a direction perpendicular to the substrate and electrically coupled to the plurality of S/D local interconnects, at least one of the plurality of vertical contacts being electrically coupled to an output signal.

### Claim 18

A semiconductor device, comprising:
a plurality of transistor pairs that are stacked over a substrate, each transistor pair of the plurality of transistor pairs including a n-type transistor and a p-type transistor that are stacked over one another;
a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs;
a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs;
one or more conductive planes formed over the substrate, the one or more conductive planes being positioned adjacent to the plurality of transistor pairs, spanning a height of the plurality of transistor pairs and being electrically coupled to the plurality of transistor pairs; and
a plurality of power rails that are positioned over the substrate and electrically coupled to the one or more conductive planes.

### Claim 19 (depends on 18)

The device of claim 18, wherein the plurality of power rails are positioned over the one or more conductive planes, each of the plurality of power rails extending along a respective power rail of the plurality of power rails so as to form a continuous connection.

### Claim 20 (depends on 18)

The device of claim 18, wherein the plurality of power rails are positioned below the one or more conductive planes, each of the one or more conductive planes either being positioned over and extending along a respective power rail of the plurality of power rails so as to form a continuous connection, or being positioned over and across two or more power rails of the plurality of power rails so as to form two or more connection points.