Integrated circuitry, memory integrated circuitry, and methods used in forming integrated circuitry

Integrated circuitry comprising:

• a three-dimensional (3D) array comprising tiers of electronic components;
• a circuit-operative stair-step structure;
• an upper landing adjacent and above the circuit-operative stair-step structure;
• the circuit-operative stair-step structure comprising:
• vertically alternating insulative tiers and conductive tiers;
• a plurality of stairs individually comprising one of the conductive tiers and one of the insulative tiers, at least some of the stairs of the plurality of stairs individually having only one of the conductive tiers and only one of the insulative tiers, the only one conductive tier extending into one of the tiers of the 3D array of the electronic components and being electrically coupled to at least one of the electronic components in that one tier;
• an uppermost of the plurality of stairs that is below the upper landing having at least one conductive tier therein that does not extend into the 3D array of the electronic components from the circuit-operative stair-step structure;
• and
• wherein a stair that is immediately under the uppermost stair has at least one conductive tier therein that does not extend into the 3D array of the electronic components from the circuit-operative stair-step structure.

Integrated circuitry comprising:

• a three-dimensional (3D) array comprising tiers of electronic components;
• a circuit-operative stair-step structure;
• an upper landing adjacent and above the circuit-operative stair-step structure;
• the circuit-operative stair-step structure comprising:
• vertically alternating insulative tiers and conductive tiers;
• a plurality of stairs individually comprising one of the conductive tiers and one of the insulative tiers, at least some of the stairs of the plurality of stairs individually having only one of the conductive tiers and only one of the insulative tiers, the only one conductive tier extending into one of the tiers of the 3D array of the electronic components and being electrically coupled to at least one of the electronic components in that one tier;
• an uppermost of the plurality of stairs that is below the upper landing having at least one conductive tier therein that does not extend into the 3D array of the electronic components from the circuit-operative stair-step structure;
• and
• wherein multiple of the stairs of the plurality of stairs that are successively immediately under the uppermost stair individually have at least one conductive tier therein that does not extend into the 3D array of the electronic components from the circuit-operative stair-step structure.

Integrated circuitry comprising:

• a three-dimensional (3D) array comprising tiers of electronic components;
• a circuit-operative stair-step structure;
• an upper landing adjacent and above the circuit-operative stair-step structure;
• and
• the circuit-operative stair-step structure comprising:
• vertically alternating insulative tiers and conductive tiers;
• a plurality of stairs individually comprising one of the conductive tiers and one of the insulative tiers, at least some of the stairs of the plurality of stairs individually having only one of the conductive tiers and only one of the insulative tiers, the only one conductive tier extending into one of the tiers of the 3D array of the electronic components and being electrically coupled to at least one of the electronic components in that one tier;
• an uppermost of the plurality of stairs that is below the upper landing having a dummy conductive tier therein;
• and
• wherein a stair that is immediately under the uppermost stair has a dummy conductive tier therein.

Integrated circuitry comprising:

• a three-dimensional (3D) array comprising tiers of electronic components;
• a circuit-operative stair-step structure;
• an upper landing adjacent and above the circuit-operative stair-step structure;
• and
• the circuit-operative stair-step structure comprising:
• vertically alternating insulative tiers and conductive tiers;
• a plurality of stairs individually comprising one of the conductive tiers and one of the insulative tiers, at least some of the stairs of the plurality of stairs individually having only one of the conductive tiers and only one of the insulative tiers, the only one conductive tier extending into one of the tiers of the 3D array of the electronic components and being electrically coupled to at least one of the electronic components in that one tier;
• an uppermost of the plurality of stairs that is below the upper landing having a dummy conductive tier therein;
• and
• wherein multiple of the stairs of the plurality of stairs that are successively immediately under the uppermost stair individually have a dummy conductive tier therein.

Memory integrated circuitry comprising:

• an array of elevationally-extending strings of memory cells individually comprising a programmable charge-storage transistor, the array comprising vertically alternating insulative tiers and wordline tiers;
• a circuitry region adjacent the array and comprising a plurality of circuit-operative stair-step structures having an upper conductive landing between and above immediately adjacent of the circuit-operative stair-step structures of the plurality of circuit-operative stair-step structures, the circuit-operative stair-step structures individually comprising:
• some of the vertically alternating insulative tiers and the wordline tiers;
• a plurality of stairs individually comprising one of the wordline tiers and one of the insulative tiers, at least some of the stairs of the plurality of stairs individually having only one of the wordline tiers and only one of the insulative tiers, the only one wordline tier of individual of the at least some of the stairs of the plurality of stairs extending into the array and being directly electrically coupled to at least one of the programmable charge-storage transistors in that one wordline tier;
• and
• at least one of the circuit-operative stair-step structures of the plurality of circuit-operative stair-step structures having an uppermost of the plurality of stairs therein that is below the upper conductive landing that is between the at least one circuit-operative stair-step structure and the circuit-operative stair-step structure of the plurality of circuit-operative stair-step structures that is immediately adjacent the at least one circuit-operative stair-step structure towards the array, said uppermost stair having a dummy wordline tier therein.

Integrated circuitry comprising:

• a three-dimensional (3D) array of electronic components;
• a circuit-operative stair-step structure electrically coupled to the electronic components of the 3D array;
• an upper landing adjacent and above the circuit-operative stair-step structure;
• the circuit-operative stair-step structure comprising:
• vertically alternating insulative tiers and conductive tiers;
• a plurality of stairs individually comprising one of the conductive tiers and one of the insulative tiers, at least some of the stairs of the plurality of stairs individually having only one of the conductive tiers and only one of the insulative tiers, the respective only ones of the conductive tiers extending into the array and directly electrically coupling with ones of the electronic components;
• and
• an uppermost of the plurality of stairs that is below the upper landing comprising at least two of the conductive tiers and at least two of the insulative tiers;
• a gap between the uppermost stair and the upper landing, the gap extending through another one of the conductive tiers that is not one of said respective only ones of the conductive tiers extending into the array;
• and
• wherein the gap comprises at least one circuit-inoperative stair-step comprising said another one conductive tier of the conductive tiers that is not one of said respective only ones of the conductive tiers extending into the array.

A method used in forming integrated circuitry, comprising:

• forming a stack of vertically alternating tiers of different composition materials;
• forming a stair-step structure into the stack and forming an upper landing adjacent and above the stair-step structure, the stair-step structure being formed to comprise:
• vertically alternating tiers of the different composition materials;
• a plurality of stairs individually comprising two of the tiers of different composition materials, at least some of the stairs of the plurality of stairs individually having only two tiers that are each only of a different one of the different composition materials;
• and
• an upper of the stairs of the plurality of stairs that is below the upper landing comprising at least four of the tiers of different composition materials;
• wherein the stairs of the plurality of stairs individually comprise a rise and a run, and
• further comprising:
• at least partially translating the stair-step structure deeper into the stack by etching deeper into the stack;
• and
• using the upper stair as masking material to preclude forming a gap between the run and the rise of an immediately adjacent of the stairs of the plurality of stairs that is below the upper stair during said etching.

Integrated circuitry comprising:

• a three-dimensional (3D) array comprising tiers of electronic components;
• a circuit-operative stair-step structure comprising a stadium comprising laterally-opposing stair flights in a vertical cross-section, one of the laterally-opposing stair flights being a circuit-operative stair flight inside the stadium, another of the laterally-opposing stair flights being a circuit-inoperative stair flight inside the stadium, laterally-opposing sides of the stadium comprising vertically alternating insulative tiers and conductive tiers;
• each of the circuit-operative stair flight inside the stadium and the circuit-inoperative stair flight inside the stadium comprising a plurality of stairs individually comprising one of the conductive tiers and one of the insulative tiers;
• at least some of the stairs of the plurality of stairs in the circuit-operative stair flight inside the stadium individually having only one of the conductive tiers and only one of the insulative tiers, the only one conductive tier extending into one of the tiers of the 3D array of the electronic components and being electrically coupled to at least one of the electronic components in that one tier;
• an upper landing adjacent and above the circuit-operative stair flight, the upper landing comprising another one of the conductive tiers or another one of the insulative tiers and that is an uppermost tier of one of the laterally-opposing sides of the stadium;
• and
• an uppermost of the plurality of stairs in the circuit-operative stair flight that is below the upper landing and that is inside the stadium having at least one conductive tier therein that does not extend into the 3D array of the electronic components from the circuit-operative stair-step structure.