# US 11,114,378 B2 · Semiconductor structure with ultra thick metal and manufacturing method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,114,378 B2
- Document ID: US11114378B2
- Status: Granted
- Kind: B2
- Application number: 16/389,500
- Filed: 2019-04-19
- Published: 2019-08-15
- Granted: 2021-09-07
- Earliest claimed: 2015-10-02
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Chen-Fa Lu; Cheng-Yuan Tsai; Ching-Chung Hsu; Chung-Long Chang
- Web page: https://patentgrep.com/patent/US11114378B2

## CPC

- H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers}
- H10P 14/46: using a liquid
- H10P 50/73: {using masks for insulating materials}
- H10P 76/204: {of organic photoresist masks}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/48: Insulating materials thereof
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.

## Claims

### Claim 1

A semiconductor structure, comprising:
a logic substrate, comprising:
a semiconductor device; and
an interconnection structure over the semiconductor device, the interconnection structure having a metal layer surrounded by a dielectric layer;
an ultra thick metal (UTM) over the metal layer, the UTM comprising a top surface; and
a photo-sensitive polymer layer surrounding the UTM, the top surface of the UTM being coplanar with a top surface of the photo-sensitive polymer layer, and the photo-sensitive polymer layer being different from the dielectric layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein UTM is positioned in a trapezoidal trench.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the UTM has a shorter side in proximity to the metal layer, an acute angle between a sidewall and an extension of the shorter side of the trapezoidal trench is in a range of from about 40 degrees to about 70 degrees.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, further comprising an isolation layer between the metal layer and the UTM.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, further comprising a via in a passivation layer above the UTM, electrically connecting the UTM and a post passivation interconnect (PPI) over the UTM.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein the PPI comprises a vertical sidewall.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein a critical dimension of a line pitch of the UTM is in a range of from about 20 μm to about 375 μm.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, further comprising a barrier layer between the UTM and the photo-sensitive polymer layer surrounding the UTM.

### Claim 9

A semiconductor structure, comprising:
a logic substrate, comprising:
a semiconductor device; and
an interconnection structure over the semiconductor device, the interconnection structure having a metal layer surrounded by a dielectric layer;
an inductor over the metal layer, comprising:
a lower metal having a top surface;
a photo-sensitive polymer layer surrounding the lower metal, the top surface of the lower metal being coplanar with a top surface of the photo-sensitive polymer layer, and the photo-sensitive polymer layer being different from the dielectric layer; and
an upper metal electrically connecting to the lower metal through a via.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, further comprising a magnetic core between the upper metal and the lower metal.

### Claim 11 (depends on 9)

The semiconductor structure of claim 9, wherein the upper metal is a post passivation interconnect (PPI) having a thickness equal to or greater than about 10 μm.

### Claim 12 (depends on 9)

The semiconductor structure of claim 9, wherein the lower metal comprises a line pattern, a cross section of the line pattern comprising an upper surface in proximity to the via and a lower surface opposite to the upper surface, a length of the upper surface being greater than a length of the lower surface.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein a ratio of one half of a length difference between the upper surface and the lower surface and the thickness of the lower metal is in a range of from about 0.8 to about 2.8.

### Claim 14 (depends on 10)

The semiconductor structure of claim 10, wherein the via and the magnetic core are in a passivation layer between the lower metal and the upper metal.

### Claim 15 (depends on 9)

The semiconductor structure of claim 9, wherein the lower metal is an ultra thick metal (UTM) with a thickness equal to or greater than 6 μm.

### Claim 16

A semiconductor structure, comprising:
a logic substrate, comprising:
a semiconductor device; and
an interconnection structure over the semiconductor device, the interconnection structure having a metal layer surrounded by a dielectric layer;
an ultra thick metal (UTM) over the metal layer;
a photo-sensitive polymer layer surrounding the UTM, and the photo-sensitive polymer layer being different from the dielectric layer; and
a seed layer between a sidewall of the UTM and the photo-sensitive polymer layer.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, where in a top surface of the UTM is coplanar with a top surface of the photo-sensitive polymer layer.

### Claim 18 (depends on 16)

The semiconductor structure of claim 16, wherein the seed layer is further between a bottom surface of the UTM and an isolation layer over the metal layer.

### Claim 19 (depends on 16)

The semiconductor structure of claim 16, further comprising a post passivation interconnect (PPI) over the UTM layer and electrically connected thereto through a via in a passivation layer.

### Claim 20 (depends on 16)

The semiconductor structure of claim 16, wherein a bottom surface of the UTM is narrower than a top surface of the UTM, an acute angle between the sidewall and an extension of the bottom surface is in a range of from about 40 degrees to about 70 degrees.