System for layout design of structure with inter layer vias
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYi-Lin Chuang, Ching-Fang Chen, Jia-Jye Shen
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Abstract
A system (including a processor and memory with computer program code) that is configured to execute a method which includes generating the layout diagram including: selecting a circuit cell which includes an active element; bundling, for purposes of placement, the circuit cell and an inter-layer via together as an integral unit; placing the integral unit of the circuit cell and the inter-layer via in a first device layer of the layout diagram; and placing a metal pattern in a second device layer of the layout diagram; and wherein the placing the integral unit of the circuit cell and the inter-layer via forms a direct electrical connection channel between the circuit cell and the metal pattern.
Claims20
A system for manufacturing a semiconductor device, the system comprising:
- at least one processor;
- and
- at least one memory including computer program code for one or more programs;
- and
- wherein, for a layout diagram stored on a non-transitory computer-readable medium, the at least one memory, the computer program code and the at least one processor are configured to cause the system to execute a method which includes generating the layout diagram including:
- selecting a circuit cell which includes an active element;
- bundling, for purposes of placement, the circuit cell and an inter-layer via together as an integral unit;
- placing the integral unit of the circuit cell and the inter-layer via in a first device layer of the layout diagram;
- and
- placing a metal pattern in a second device layer of the layout diagram;
- and
- wherein the placing the integral unit of the circuit cell and the inter-layer via forms a direct electrical connection channel between the circuit cell and the metal pattern.
A system for manufacturing a semiconductor device, the system comprising:
- at least one processor;
- and
- at least one memory including computer program code for one or more programs;
- and
- wherein, for a layout diagram stored on a non-transitory computer-readable medium, the at least one memory, the computer program code and the at least one processor are configured to cause the system to execute a method which includes generating the layout diagram including:
- placing a power supply rail pattern in a first device layer of the layout diagram;
- selecting a circuit cell which includes an active element;
- bundling the circuit cell and one or more inter-layer vias together as an integral unit;
- and
- placing the integral unit of the circuit cell and the one or more inter-layer vias in the first device layer of the layout diagram such that one or more metal line patterns in the circuit cell are located parallel to albeit without overlapping the power supply rail pattern;
- and
- wherein the placing the integral unit of the circuit cell and the one or more inter-layer vias forms a direct electrical connection channel between the circuit cell and a metal pattern in a second device layer of the layout diagram.
A system for manufacturing a semiconductor device, the system comprising:
- at least one processor;
- and
- at least one memory including computer program code for one or more programs;
- and
- wherein, for a layout diagram stored on a non-transitory computer-readable medium, the at least one memory, the computer program code and the at least one processor are configured to cause the system to execute a method which includes generating the layout diagram including:
- selecting an inter-layer via which has a footprint which is at least one factor of ten smaller than a footprint of a corresponding circuit cell;
- bundling the inter-layer via and the corresponding circuit cell together as an integral unit;
- placing the integral unit of the inter-layer via and the corresponding circuit cell in a first device layer of the layout diagram, the first device layer including at least one active component;
- placing a connection between the corresponding circuit cell and a power supply rail within the first device layer;
- and
- wherein the placing the integral unit of the inter-layer via and the corresponding circuit cell forms a direct electrical connection channel between the first device layer and a second device layer of the layout diagram which thereby provides a level-shifted version of voltage on the power supply rail from the first device layer to the second device layer.
Dependencies are inferred from the claim text.