# US 11,114,370 B2 · Semiconductor device packages and methods of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,114,370 B2 - Document ID: US11114370B2 - Status: Granted - Kind: B2 - Application number: 16/675,013 - Filed: 2019-11-05 - Published: 2021-05-06 - Granted: 2021-09-07 - Earliest claimed: 2019-11-05 - Assignees: Advanced Semiconductor Engineering, Inc. - Applicants: Advanced Semiconductor Engineering, Inc. - Inventors: Shun-Tsat Tu; Hong-Jyun Lin; Yi Tong Chiu; Yi Chun Wu - Web page: https://patentgrep.com/patent/US11114370B2 ## CPC - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating} - H10W 20/068: {by using a laser, e.g. laser cutting or laser direct writing} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/6525: {for securing the interconnections to the substrate, e.g. to prevent peeling} - H10W 70/66: Conductive materials thereof - H10W 70/685: comprising multiple insulating layers - H10W 72/30: Die-attach connectors - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device package includes a substrate, a redistribution structure, a conductive pad, a conductive element, and a conductive via. The redistribution structure is disposed over the substrate and includes a first dielectric layer and a first conductive layer. The conductive pad is disposed on a first surface of the first dielectric layer. The conductive element is disposed in the first dielectric layer and is electrically connected to the conductive pad. The conductive via extends from the conductive pad toward the substrate through the conductive element and the first dielectric layer. The first conductive layer is separated from the conductive via. ## Claims ### Claim 1 A semiconductor device package, comprising: a substrate; a redistribution structure disposed over the substrate and including a first dielectric layer and a first conductive layer; a conductive pad disposed on a first surface of the first dielectric layer; a conductive element disposed in the first dielectric layer and electrically connected to the conductive pad; and a conductive via extending from the conductive pad toward the substrate through the conductive element and the first dielectric layer, wherein the first conductive layer is separated from the conductive via, wherein the redistribution structure further comprises: a second dielectric layer disposed between the first dielectric layer and the substrate; and a second conductive layer disposed in the first dielectric layer and the second dielectric layer, and electrically connected to the conductive element; wherein the conductive via extends through the second dielectric layer and, wherein the second conductive layer is separated from the conductive via. ### Claim 2 (depends on 1) The semiconductor device package of claim 1, wherein the first conductive layer directly contacts the conductive element. ### Claim 3 (depends on 1) The semiconductor device package of claim 1, wherein the conductive pad is separated from the conductive element. ### Claim 4 (depends on 1) The semiconductor device package of claim 1, wherein the first conductive layer comprises: a first portion substantially disposed on a second surface of the first dielectric layer; a third portion, disposed at a higher elevation than the first portion with respect to the substrate, wherein the first portion and the third portion extends in a direction different from that of the conductive via. ### Claim 5 (depends on 4) The semiconductor device package of claim 4, wherein the first conductive layer further comprises: a second portion extending in a direction substantially parallel to that of the conductive via, wherein the second portion connects the first portion and the third portion. ### Claim 6 (depends on 5) The semiconductor device package of claim 5, wherein the first conductive layer further includes a seed layer substantially conformal with first portion, second portion and third portion. ### Claim 7 (depends on 1) The semiconductor device package of claim 1, wherein the conductive via is electrically connected with the first conductive layer through the conductive element. ### Claim 8 (depends on 1) The semiconductor device package of claim 1, wherein the conductive element encloses a top portion of the conductive via. ### Claim 9 (depends on 1) The semiconductor device package of claim 1, further comprising a first seed layer disposed on the first surface of the first dielectric layer and a second surface of the conductive element; and a second seed layer having a smooth contour of a lateral surface of the conductive via. ### Claim 10 (depends on 1) The semiconductor device package of claim 1, wherein the conductive via has a lateral surface traversing through a single material along a thickness of the redistribution structure. ### Claim 11 (depends on 1) The semiconductor device package of claim 1, wherein the first conductive element has a ring or ring-like structure. ### Claim 12 (depends on 1) The semiconductor device package of claim 1, further comprising: a third dielectric layer disposed on the second dielectric layer and the substrate; a third conductive layer disposed in the first dielectric layer, the second dielectric layer, and the third dielectric layer, and electrically connected to the conductive element; wherein the conductive via extends through the third dielectric layer and, wherein the third conductive layer is separated from the conductive via. ### Claim 13 A semiconductor device package, comprising: a substrate; a first dielectric layer having a top surface, a bottom surface, and a lateral surface disposed over the substrate; a conductive element disposed in the first dielectric layer; a first conductive layer disposed on the bottom surface and the lateral surface of the first dielectric layer and electrically connected with the conductive element; a conductive via disposed on the substrate; a second dielectric layer disposed between the first conductive layer and the conductive via; a third dielectric layer disposed on the bottom surface of the first dielectric layer and having a bottom surface and a lateral surface; a fourth dielectric layer disposed between the second conductive layer and the conductive via; and a second conductive layer disposed on the bottom surface and the lateral surface of the third dielectric layer, wherein the second dielectric layer encloses the conductive via, and wherein the first conductive layer has a portion extending toward the conductive via along a bottom surface of the conductive element, wherein the second conductive layer extends through the second dielectric layer and is electrically connected with the conductive element, and wherein the fourth dielectric layer encloses the conductive via. ### Claim 14 (depends on 13) The semiconductor device package of claim 13, further comprising a first conductive pad extending along the top surface of the first dielectric layer, wherein the first conductive pad is electrically connected to the conductive via and the conductive element. ### Claim 15 (depends on 13) The semiconductor device package of claim 13, wherein the conductive element has an inner lateral surface in electrical contact with the conductive via and an outer lateral surface in contact with the first dielectric layer.