# US 11,114,366 B2 · Semiconductor structure with buried conductive line and method for forming the same

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- Number: US 11,114,366 B2
- Document ID: US11114366B2
- Status: Granted
- Kind: B2
- Application number: 16/589,263
- Filed: 2019-10-01
- Published: 2021-04-01
- Granted: 2021-09-07
- Earliest claimed: 2019-10-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jhon-Jhy Liaw
- Web page: https://patentgrep.com/patent/US11114366B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/121: {oriented parallel to substrates}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor structure is provided. The semiconductor structure includes a first well region over a substrate, and an isolation structure over the first well region. The semiconductor structure also includes a first transistor over the first well region, and a first buried conductive line over the first well region and electrically connected to a source structure of the first transistor. A top surface of the first buried conductive line is substantially level with or lower than a top surface of the isolation structure.

## Claims

### Claim 1

A semiconductor structure, comprising:
a first well region over a substrate;
an isolation structure over the first well region;
a first transistor over the first well region, wherein the first transistor comprises a gate structure and a gate spacer over sidewalls of the gate structure; and
a first buried conductive line over the first well region and electrically connected to a source structure of the first transistor, wherein a top surface of the first buried conductive line is substantially level with or lower than a top surface of the isolation structure, and wherein a portion of the first buried conductive line is covered by the gate spacer.

### Claim 2 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the first transistor further comprises:
a fin structure protruding from the isolation structure, wherein the fin structure is covered by the gate structure.

### Claim 3 (depends on 1)

The semiconductor structure as claimed in claim 1, further comprising:
a second well region over the substrate, wherein the second well region adjoins the first well region, and the isolation structure is over the second well region;
a second transistor over the second well region; and
a second buried conductive line over the second well region and electrically connected to a source structure of the second transistor, wherein the second buried conductive line is parallel to the first buried conductive line.

### Claim 4 (depends on 3)

The semiconductor structure as claimed in claim 3, wherein the first well region is p-type and the second well region is n-type, and
wherein the first buried conductive line is embedded in the isolation structure, and a portion of the isolation structure is sandwiched between the second buried conductive line and the second well region.

### Claim 5 (depends on 3)

The semiconductor structure as claimed in claim 3, wherein the first well region is p-type and the second well region is n-type, and
wherein the first buried conductive line and the second buried conductive line are embedded in the isolation structure and contact the first well region and the second well region respectively.

### Claim 6 (depends on 1)

The semiconductor structure as claimed in claim 1, further comprising:
a first contact over the source structure of the first transistor, wherein the source structure of the first transistor is electrically connected to the first buried conductive line through the first contact.

### Claim 7

A semiconductor structure, comprising:
an N-type well region and a P-type well region over a substrate, wherein the P-type well region adjoins the N-type well region;
an isolation structure over the N-type well region and the P-type well region;
a PMOS transistor and a first buried conductive line over the N-type well region, wherein a portion of the isolation structure is sandwiched between the first buried conductive line and the N-type well region;
a first contact over a source structure of the PMOS transistor, wherein a portion of the first buried conductive line overlaps the first contact; and
an NMOS transistor and a second buried conductive line over the P-type well region, wherein the PMOS transistor and the NMOS transistor share a gate structure.

### Claim 8 (depends on 7)

The semiconductor structure as claimed in claim 7, wherein the first buried conductive line is electrically connected to the source structure of the PMOS transistor through the first contact, and a bottom surface of the first buried conductive line is higher than a bottom surface of the isolation structure.

### Claim 9 (depends on 7)

The semiconductor structure as claimed in claim 7, further comprising:
a second contact over a source structure of the NMOS transistor, wherein the second buried conductive line is electrically connected to the source structure of the NMOS transistor through the second contact, and a portion of the second buried conductive line is covered by the second contact.

### Claim 10 (depends on 7)

The semiconductor structure as claimed in claim 7, further comprising:
an inter-layer dielectric (ILD) structure surrounding the first contact; and
a strap structure over the ILD structure and electrically connected to the first contact, wherein the strap structure comprises a first via, a first conductive line over the first via, a second via over the first conductive line, and a second conductive line over the second via.

### Claim 11 (depends on 10)

The semiconductor structure as claimed in claim 10, wherein the PMOS transistor, the NMOS transistor and the strap structure are arranged in a logic cell, and the strap structure overlaps the first contact in a top view.

### Claim 12 (depends on 10)

The semiconductor structure as claimed in claim 10, further comprising:
a logic cell, wherein the PMOS transistor and the NMOS transistor are arranged in the logic cell; and
a filler cell adjacent to the logic cell, wherein the filler cell is between a first dielectric-base dummy gate and a second dielectric-base dummy gate, and the strap structure is arranged in the filler cell in a top view.

### Claim 13

A method for forming a semiconductor structure, comprising:
forming a first well region in a substrate;
forming a first fin structure over the first well region;
forming an isolation structure over the first well region, wherein the first fin structure protrudes from the isolation structure;
partially removing the isolation structure to form a first trench over the first well region, wherein the first trench and the first fin structure are parallel to each other, and the first well region is exposed by the first trench;
forming a first buried conductive line in the first trench, wherein the first buried conductive line extends into a top portion of the first well region; and
forming a first transistor over the first well region after the first buried conductive line is formed, wherein the first buried conductive line is electrically connected to a source structure of the first transistor.

### Claim 14 (depends on 13)

The method for forming the semiconductor structure as claimed in claim 13, further comprising:
forming a dielectric capping layer covering the first buried conductive line and the isolation structure before the source structure of the first transistor is formed.

### Claim 15 (depends on 13)

The method for forming the semiconductor structure as claimed in claim 13, further comprising:
forming a second well region adjacent to the first well region;
forming a second fin structure over the second well region, wherein the second fin structure protrudes from the isolation structure;
partially removing the isolation structure to form a second trench over the second well region, wherein the second trench is parallel to the first trench;
forming a second buried conductive line in the second trench; and
forming a second transistor over the second well region after the second buried conductive line is formed, wherein the second buried conductive line is electrically connected to a source structure of the second transistor.

### Claim 16 (depends on 15)

The method for forming the semiconductor structure as claimed in claim 15, wherein the first transistor is an NMOS, the second transistor is a PMOS, and a bottom surface of the second trench is higher than a bottom surface of the first trench.

### Claim 17 (depends on 15)

The method for forming the semiconductor structure as claimed in claim 15, wherein forming the first transistor further comprises:
forming a dummy gate structure across the first fin structure and the second fin structure; and
forming a gate spacer surrounding the dummy gate structure before the source structure of the first transistor is formed, wherein the first buried conductive line and the second buried conductive line are partially covered by the gate spacer.

### Claim 18 (depends on 13)

The method for forming the semiconductor structure as claimed in claim 13, further comprising:
forming an inter-layer dielectric (ILD) structure covering the source structure of the first transistor;
partially removing the ILD structure to expose the first buried conductive line, and the source structure of the first transistor; and
forming a first contact over the source structure of the first transistor, wherein the source structure of the first transistor is electrically connected to the first buried conductive line through the first contact.

### Claim 19 (depends on 18)

The method for forming the semiconductor structure as claimed in claim 18, further comprising:
forming a first dielectric layer over the ILD structure;
forming a first via penetrating through the first dielectric layer;
forming a second dielectric layer over the first dielectric layer;
forming a first conductive line penetrating through the second dielectric layer, wherein the first conductive line is parallel to the first buried conductive line;
forming a third dielectric layer over the second dielectric layer; and
forming a second via penetrating through the third dielectric layer, wherein the second via is electrically connected to the first contact through the first conductive line and the first via.

### Claim 20 (depends on 13)

The method for forming the semiconductor structure as claimed in claim 13, wherein the first buried conductive line is not connected to a drain structure of the first transistor.