# US 11,114,359 B2 · Wafer level chip scale package structure

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- Number: US 11,114,359 B2
- Document ID: US11114359B2
- Status: Granted
- Kind: B2
- Application number: 16/130,378
- Filed: 2018-09-13
- Published: 2020-03-19
- Granted: 2021-09-07
- Earliest claimed: 2018-09-13
- Assignees: Dialog Semiconductor (UK) Limited
- Applicants: Dialog Semiconductor (UK) Limited
- Inventors: Jesus Mennen Belonio, Jr.; Shou Cheng Eric Hu; Ian Kent; Ernesto Gutierrez, III; Jerry Li
- Web page: https://patentgrep.com/patent/US11114359B2

## CPC

- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/43: Layouts of interconnections
- H10W 20/4424: {Copper alloys}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 46/301: {for alignment}
- H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07323: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 90/00: Package configurations
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

At least one redistribution layer (RDL) is provided on a silicon die. A passivation layer is deposited on the RDL. First openings having a first diameter are etched in the passivation layer where copper posts are to be formed. A seed layer is deposited over the passivation layer and within the openings. A photoresist layer is coated on the seed layer and patterned to form second openings having a second diameter over the first openings larger than the first diameter. Copper is plated on the seed layer to form copper posts filling the second openings. The silicon die is die attached to a metal substrate. A lamination layer is coated over the silicon die and the copper posts. Third openings are formed through the lamination layer to the copper posts and to metal pads on the metal substrate. Metal vias are formed in the third openings.

## Claims

### Claim 1

A wafer level chip scale package comprising:
a silicon die, comprising:
at least one redistribution layer (RDL);
a passivation layer on said RDL; and
at least one copper post at a top surface of said silicon die, said at least one copper post contacting said at least one RDL through an opening in said passivation layer to said at least one RDL wherein said at least one copper post has a larger diameter than a diameter of said opening to said at least one RDL;
wherein a bottom surface of said silicon die is die attached to a metal substrate comprising:
a solder substrate;
a copper layer on said solder substrate;
a copper or nickel-plated layer on said copper layer; and
a stopper layer on said copper or nickel-plated layer comprising epoxy-based composite or pre-impregnated composite fiber (PP) materials wherein said silicon die is above said copper or nickel-plated layer and said stopper layer lies between said silicon die and said copper or nickel-plated layer to prevent copper or nickel from penetrating into said silicon die; and
metal vias through a lamination layer spaced from sidewall of said copper layer by said copper or nickel-plated layer on sidewalls of said copper layer, on sidewalls and overlying said silicon die, and overlying said metal substrate, said metal vias providing connections to said at least one copper post on said silicon die and to at least one metal pad on said metal substrate.

### Claim 2 (depends on 1)

The package according to claim 1 wherein said lamination layer comprises an epoxy-based composite, pre-impregnated composite fiber (PP) materials, or resin.

### Claim 3 (depends on 1)

The package according to claim 1 further comprising a solder mask over said metal vias.

### Claim 4

A method of fabricating a wafer level chip scale package comprising:
providing at least one redistribution layer (RDL) on a silicon substrate;
depositing a passivation layer on said RDL;
etching first openings having a first diameter in said passivation layer where copper posts are to be formed;
depositing a seed layer over said passivation layer and within said openings;
coating a photoresist layer on said seed layer and patterning said photoresist layer to form second openings having a second diameter over said first openings wherein said second diameter is larger than said first diameter;
plating copper on said seed layer in said first and second openings to form said copper posts filling said second openings to complete formation of a silicon die;
thereafter die attaching said silicon die to a metal substrate;
coating a lamination layer over said metal substrate, said silicon die, and said copper posts;
forming third openings through said lamination layer to said copper posts and to metal pads on said metal substrate;
forming metal vias in said third openings; and
covering said metal vias with a solder mask to complete said wafer level chip scale package.

### Claim 5 (depends on 4)

The method according to claim 4 wherein said passivation layer comprises polybenzoxazole (PBO) or polyimide (PI).

### Claim 6 (depends on 4)

The method according to claim 4 wherein said copper posts have a thickness of between about 1 μm and 100 μm, and preferably about 1 μm and 20 μm.

### Claim 7 (depends on 4)

The method according to claim 4 further comprising:
depositing an organic solderability preservative (OSP) layer onto said copper posts prior to said die attaching step; and
removing said OSP layer in said third openings prior to forming said metal vias.

### Claim 8 (depends on 4)

The method according to claim 4 wherein said metal substrate comprises:
a solder substrate,
a copper layer on said solder substrate;
a copper or nickel-plated layer deposited on said copper layer; and
a stopper layer on said copper or nickel-plated layer comprising epoxy-based composite or pre-impregnated composite fiber (PP) materials.

### Claim 9 (depends on 4)

The method according to claim 4 wherein said lamination layer comprises an epoxy-based composite, pre-impregnated composite fiber (PP) materials, or resin.

### Claim 10

A method of fabricating a wafer level chip scale package comprising:
providing at least one redistribution layer (RDL) on a silicon substrate;
depositing a passivation layer on said RDL;
etching first openings having a first diameter in said passivation layer where copper posts are to be formed;
depositing a seed layer over said passivation layer and within said openings;
coating a photoresist layer on said seed layer and patterning said photoresist layer to form second openings having a second diameter over said first openings wherein said second diameter is larger than said first diameter;
plating copper on said seed layer in said first and second openings to form said copper posts filling said second openings to complete formation of a silicon die;
providing a metal substrate comprising:
providing a solder substrate;
depositing a copper layer on said solder substrate;
depositing a copper or nickel-plated layer on said copper layer; and
forming a stopper layer on said copper or nickel-plated layer comprising epoxy-based composite or pre-impregnated composite fiber (PP) materials;
thereafter die attaching said silicon die to said metal substrate;
coating a lamination layer over said metal substrate, said silicon die, and said copper posts;
forming third openings through said lamination layer to said copper posts and to metal pads on said metal substrate;
forming metal vias in said third openings; and
covering said metal vias with a solder mask to complete said wafer level chip scale package.

### Claim 11 (depends on 10)

The method according to claim 10 wherein said passivation layer comprises polybenzoxazole (PBO) or polyimide (PI).

### Claim 12 (depends on 10)

The method according to claim 10 wherein said copper posts have a thickness of between about 1 μm and 100 μm, and preferably about 1 μm and 20 μm.

### Claim 13 (depends on 10)

The method according to claim 10 further comprising:
depositing an organic solderability preservative (OSP) layer onto said copper posts prior to said die attaching step; and
removing said OSP layer in said third openings prior to forming said metal vias.

### Claim 14 (depends on 10)

The method according to claim 10 wherein said lamination layer comprises an epoxy-based composite, pre-impregnated composite fiber (PP) materials, or resin.