Dummy element and method of examining defect of resistive element
AssigneeFuji Electric Co., Ltd.
InventorsOsamu Sasaki, Masaru Saito, Taichi Karino
Life of this patent
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AssigneeFuji Electric Co., Ltd.
InventorsOsamu Sasaki, Masaru Saito, Taichi Karino
Estimating the term…
A dummy element includes: a semiconductor substrate; a lower insulating film deposited on the semiconductor substrate; a first resistive layer deposited on the lower insulating film; an interlayer insulating film covering the first resistive layer; a first pad-forming electrode deposited on the interlayer insulating film so as to be connected to the first resistive layer, and including an extending portion to be in Schottky contact with the semiconductor substrate; a relay wire connected to the first resistive layer and connected to the semiconductor substrate with an ohmic contact; and a counter electrode allocated under the semiconductor substrate, the dummy element simulating a defective state in the lower insulating film and the interlayer insulating film immediately under the first pad-forming electrode included in a corresponding resistive element as a target to be examined.
A dummy element for simulating a defective state of a resistive element of a target to be examined, the dummy element comprising:
A method of examining a defect of a resistive element of a target, using a dummy element including a lower insulating film deposited on a semiconductor substrate, a first resistive layer deposited on the lower insulating film, an interlayer insulating film covering the first resistive layer, a first pad-forming electrode deposited on the interlayer insulating film and having a contact portion in direct contact with the first resistive layer and an extending portion to be in Schottky contact with the semiconductor substrate so as to cause a short circuit between the first pad-forming electrode and the semiconductor substrate to simulate a Schottky contact state, a relay wire connected to the first resistive layer and connected to the semiconductor substrate with an ohmic contact, and a counter electrode allocated under the semiconductor substrate, the method comprising:
A dummy element for simulating a defective state of a resistive element of a target to be examined, the dummy element comprising:
Dependencies are inferred from the claim text.