# US 11,114,346 B2 · High density logic formation using multi-dimensional laser annealing

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- Number: US 11,114,346 B2
- Document ID: US11114346B2
- Status: Granted
- Kind: B2
- Application number: 16/705,485
- Filed: 2019-12-06
- Published: 2021-02-11
- Granted: 2021-09-07
- Earliest claimed: 2019-08-06
- Assignees: Tokyo Electron Limited
- Applicants: Tokyo Electron Limited
- Inventors: H. Jim Fulford; Mark I. Gardner; Jeffrey Smith; Lars Liebmann; Daniel Chanemougame
- Web page: https://patentgrep.com/patent/US11114346B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 88/01: {Manufacture or treatment}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3456: {Polycrystalline}
- H10P 14/3808: {using laser beams}
- H10P 14/6349: {Deposition of epitaxial materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.

## Claims

### Claim 1

A method of forming transistor devices, the method comprising:
forming a first transistor plane as a transistor-based circuit device on a substrate, the circuit device including a plurality of field effect transistors;
depositing a first insulator layer on the first transistor plane;
depositing a first layer of polycrystalline silicon on the first insulator layer; and
annealing the first layer of polycrystalline silicon using laser heating, the laser heating increasing grain size of the first layer of polycrystalline silicon to form a first epitaxial-like silicon layer having a crystal orientation that is independent from the substrate.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a second transistor plane on the first epitaxial-like silicon layer, the second transistor plane including channels of field effect transistors;
depositing a second insulator layer on the second transistor plane;
depositing a second layer of polycrystalline silicon on the second insulator layer; and
annealing the second layer of polycrystalline silicon using laser heating, the laser heating increasing grain size of the second layer of polycrystalline silicon to form a second epitaxial-like silicon layer having a crystal orientation that is independent from the crystal orientation for the first epitaxial-like silicon layer.

### Claim 3 (depends on 2)

The method of claim 2, further comprising planarizing the first layer of polycrystalline silicon prior to depositing the second transistor plane.

### Claim 4 (depends on 2)

The method of claim 2, where the first transistor plane includes multiple levels of transistors in which one field-effect transistor is positioned directly above a second field effect transistor.

### Claim 5 (depends on 1)

The method of claim 1, wherein annealing the first layer of polycrystalline silicon includes increasing a grain size sufficient to convert the first layer of polycrystalline silicon to a monocrystalline silicon film.

### Claim 6 (depends on 1)

The method of claim 1, wherein the annealing the first layer of polycrystalline silicon using laser heating is performed such that the heating amount and duration is targeted to the polycrystalline silicon and the underlying layers are not heated above a predetermined temperature.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
growing alternating SiGe and Si layers on the first layer of polycrystalline silicon converted to epitaxial silicon.

### Claim 8 (depends on 1)

The method of claim 1, wherein the annealing the first layer of polycrystalline silicon using laser heating includes laser heating with chilled water as a medium between the laser beam and the first layer of polycrystalline silicon.

### Claim 9 (depends on 1)

The method of claim 1, wherein the substrate is held by a wafer chuck, and
wherein the annealing the first layer of polycrystalline silicon using laser heating includes laser heating while the first layer of polycrystalline silicon is in a cryogenic coolant.

### Claim 10 (depends on 9)

The method of claim 9, wherein the cryogenic coolant is at a temperature in a range of 400K to 30K.

### Claim 11

A method of forming transistor devices, the method comprising:
forming a first transistor plane as a transistor-based circuit device on a substrate, the first circuit device including channels of field effect transistors;
depositing a first insulator layer on the first transistor plane;
depositing a first layer of polycrystalline silicon on the first insulator layer;
annealing the first layer of polycrystalline silicon using laser heating, the laser heating increasing grain size of the first layer of polycrystalline silicon and having a crystal orientation that is independent from the substrate;
forming a second transistor plane as a second transistor-based circuit device on the first layer of polycrystalline silicon having the increased grain size, the second circuit device having channels of field effect transistors;
depositing a second insulator layer on the second transistor plane;
depositing a second layer of polycrystalline silicon on the second insulator layer; and
annealing the second layer of polycrystalline silicon using laser heating, the laser heating increasing grain size of the second layer of polycrystalline silicon and having a crystal orientation that is independent from the crystal orientation for the first layer of polycrystalline silicon having the increased grain size.

### Claim 12 (depends on 11)

The method of claim 11, wherein the first transistor plane includes multiple epitaxial films sufficient to form one field-effect transistor positioned directly above a second field effect transistor.

### Claim 13 (depends on 11)

The method of claim 11, further comprising, forming a first etch mask on the substrate and using the first etch mask to etch both the first transistor plane and the second transistor plane.

### Claim 14 (depends on 11)

The method of claim 11, wherein annealing the first layer of polycrystalline silicon includes increasing a grain size sufficient to convert the first layer of polycrystalline silicon to a monocrystalline silicon film.

### Claim 15 (depends on 11)

The method of claim 11, where the second transistor plane includes multiple levels of transistors in which one field-effect transistor is positioned directly above a second field effect transistor.

### Claim 16 (depends on 11)

The method of claim 11, wherein the annealing the first layer of polycrystalline silicon using laser heating is performed such that the heating amount and duration is targeted to the polysilicon silicon and the underlying layers are not heated above a predetermined temperature.

### Claim 17 (depends on 11)

The method of claim 11, further comprising:
growing alternating SiGe and Si layers on the second layer of polycrystalline silicon converted to epitaxial silicon.

### Claim 18 (depends on 11)

The method of claim 11, wherein the annealing the second layer of polycrystalline silicon using laser heating includes laser heating with chilled water as a medium between the laser beam and the second layer of polycrystalline silicon.

### Claim 19 (depends on 11)

The method of claim 11, wherein the substrate is held by a wafer chuck, and
wherein the annealing the second layer of polycrystalline silicon using laser heating includes laser heating while the second layer of polycrystalline silicon is in a cryogenic coolant.

### Claim 20 (depends on 19)

The method of claim 19, wherein the cryogenic coolant is at a temperature in a range of 400K to 30K.