# US 11,114,345 B2 · IC including standard cells and SRAM cells

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- Number: US 11,114,345 B2
- Document ID: US11114345B2
- Status: Granted
- Kind: B2
- Application number: 16/548,285
- Filed: 2019-08-22
- Published: 2021-02-25
- Granted: 2021-09-07
- Earliest claimed: 2019-08-22
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jhon-Jhy Liaw
- Web page: https://patentgrep.com/patent/US11114345B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10B 10/18: {Peripheral circuit regions}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/834: further characterised by the dopants
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/6903: {containing silicon}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 84/907: {CMOS gate arrays}
- H10D 84/966: {Gate electrode terminals or contacts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

An IC is provided. The IC includes a plurality of P-type gate-all-around (GAA) field-effect transistors (FETs). At least one first P-type GAA FET includes a plurality of silicon (Si) channel regions vertically stacked over an N-type well region. At least one second P-type GAA FET includes a plurality of silicon germanium (SiGe) channel regions vertically stacked over the N-type well region.

## Claims

### Claim 1

An integrated circuit (IC), comprising:
a plurality of P-type gate-all-around (GAA) field-effect transistors (FETs), comprising:
at least one first P-type GAA FET comprising a plurality of silicon (Si) channel regions vertically stacked over an N-type well region; and
at least one second P-type GAA FET comprising a plurality of silicon germanium (SiGe) channel regions vertically stacked over the N-type well region;
at least one SRAM memory cell comprising the first P-type GAA FET; and
at least one standard cell or I/O cell comprising the second P-type GAA FET.

### Claim 2 (depends on 1)

The IC as claimed in claim 1, wherein each of the SiGe channel regions comprises Si-base semiconductor nanowire or nanosheet and SiGe or Ge epitaxy growth material, wherein the Si-base semiconductor nanowire or nanosheet is surrounded by the SiGe or Ge epitaxy growth material.

### Claim 3 (depends on 2)

The IC as claimed in claim 2, wherein the SiGe or Ge epitaxy growth material of each of the SiGe channel regions is surrounded by a gate electrode of the second P-type GAA FET.

### Claim 4 (depends on 1)

The IC as claimed in claim 1, wherein a first space between two adjacent Si channel regions vertically stacked and a second space between two adjacent SiGe channel regions vertically stacked are substantially the same.

### Claim 5 (depends on 1)

The IC as claimed in claim 1, wherein in the second P-type GAA FET, Ge atomic concentration in the SiGe channel regions is in a range from about 5% to about 35%.

### Claim 6 (depends on 1)

The IC as claimed in claim 1, wherein source and drain regions of the first P-type GAA FET and the second P-type GAA FET are formed by SiGe with Boron epitaxy growth material.

### Claim 7 (depends on 1)

The IC as claimed in claim 1, further comprising:
a plurality of N-type GAA FETs,
wherein each of the N-type GAA FETs comprises a plurality of Si channel regions vertically stacked over a P-type well region, and source and drain regions of the N-type GAA FETs comprise SiP, SiC, SiPC, SiAs, Si, or a combination thereof.

### Claim 8

An integrated circuit (IC), comprising:
a first P-type gate-all-around (GAA) field-effect transistor (FET) comprising a plurality of first silicon (Si) channel regions vertically stacked over a substrate;
a second P-type GAA FET comprising a plurality of first silicon germanium (SiGe) channel regions vertically stacked over the substrate; and
a third P-type GAA FET comprising a plurality of second SiGe channel regions vertically stacked over the substrate,
wherein the second SiGe channel regions are surrounded by a first gate electrode,
wherein a gate dielectric layer is formed between the second SiGe channel regions and the first gate electrode, and the gate dielectric layer comprises Lanthanum-doped (La-doped) dielectric material,
wherein threshold voltages of the first, second and third P-type GAA FETs are different.

### Claim 9 (depends on 8)

The IC as claimed in claim 8, further comprising:
a fourth P-type GAA FET comprising a plurality of second Si channel regions vertically stacked over the substrate,
wherein the second Si channel regions are surrounded by a second gate electrode,
wherein a gate dielectric layer is formed between the second Si channel regions and the second gate electrode, and the gate dielectric layer comprises La-doped dielectric material.

### Claim 10 (depends on 8)

The IC as claimed in claim 8, wherein the threshold voltage of the first P-type GAA FET is greater than the threshold voltage of the third P-type GAA FET, and the threshold voltage of the third P-type GAA FET is greater than the threshold voltage of the second P-type GAA FET.

### Claim 11 (depends on 8)

The IC as claimed in claim 8, further comprising:
at least one SRAM memory cell comprising the first P-type GAA FET;
at least one first standard cell comprising the second P-type GAA FET; and
at least one second standard cell comprising the third P-type GAA FET.

### Claim 12 (depends on 8)

The IC as claimed in claim 8, further comprising:
at least one I/O cell comprising the first P-type GAA FET;
at least one first standard cell comprising the second P-type GAA FET; and
at least one second standard cell comprising the third P-type GAA FET.

### Claim 13 (depends on 8)

The IC as claimed in claim 8, wherein source and drain regions of the first, second and third P-type GAA FETs are formed by SiGe with Boron epitaxy growth material.

### Claim 14 (depends on 8)

The IC as claimed in claim 8, further comprising:
a plurality of first N-type GAA FETs,
wherein each of the first N-type GAA FETs comprises a plurality of third Si channel regions vertically stacked over the substrate, and source and drain regions of the first N-type GAA FETs comprise SiP, SiC, SiPC, SiAs, Si, or a combination thereof.

### Claim 15 (depends on 8)

The IC as claimed in claim 8, wherein the first SiGe channel regions are surrounded by a third gate electrode, wherein a gate dielectric layer is formed between the first SiGe channel regions and the third gate electrode, and the gate dielectric layer is free of La-doped dielectric material.

### Claim 16

An integrated circuit (IC), comprising:
a plurality of cells arranged in an array, comprising:
a first cell, comprising at least one first P-type gate-all-around (GAA) field-effect transistor (FET) having a plurality of silicon (Si) channel regions vertically stacked over an N-type well region;
a second cell, comprising at least one second P-type GAA FET having a plurality of first silicon germanium (SiGe) channel regions vertically stacked over the N-type well region; and
a third cell, comprising at least one third P-type GAA FET having a plurality of second SiGe channel regions vertically stacked over the N-type well region,
wherein Ge atomic concentration in the first SiGe channel regions is different from Ge atomic concentration in the second SiGe channel regions.

### Claim 17 (depends on 16)

The IC as claimed in claim 16, wherein the first, second and third cells are arranged in one row of the array.

### Claim 18 (depends on 16)

The IC as claimed in claim 16, wherein Ge atomic concentration in the first SiGe channel regions is in a range from about 15% to about 35%, and Ge atomic concentration of the second SiGe channel regions is in a range from about 5% to about 14.5%.

### Claim 19 (depends on 16)

The IC as claimed in claim 16, wherein a first space between two adjacent first SiGe channel regions vertically stacked and a second space between two adjacent second SiGe channel regions vertically stacked are substantially the same.

### Claim 20 (depends on 16)

The IC as claimed in claim 16, wherein each of the first, second and third cells further comprises:
at least one N-type GAA FET,
wherein the N-type GAA FET comprises a plurality of Si channel regions vertically stacked over a P-type well region, and source and drain regions of the N-type GAA FETs comprise SiP, SiC, SiPC, SiAs, Si, or a combination thereof.