# US 11,114,337 B2 · Method for bonding and interconnecting semiconductor chips

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- Number: US 11,114,337 B2
- Document ID: US11114337B2
- Status: Granted
- Kind: B2
- Application number: 16/716,025
- Filed: 2019-12-16
- Published: 2020-06-25
- Granted: 2021-09-07
- Earliest claimed: 2018-12-19
- Assignees: Imec Vzw
- Applicants: Imec Vzw
- Inventors: Gaspard Hiblot; Julien Jussot; Geert Van der Plas
- Web page: https://patentgrep.com/patent/US11114337B2

## CPC

- H10P 90/1914: {using bonding}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0253: {comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2125: {Top-view shapes}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/0198: {batch processes}
- H10W 72/90: Bond pads, in general
- H10W 90/00: Package configurations
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method is provided for bonding and interconnecting two semiconductor chips arranged on semiconductor substrates. HSQ (Hydrogen Silsesquioxane) or an equivalent material is used as a bonding layer and after bonding and thinning one of the wafers (or first thinning and then bonding), the bond layer is locally irradiated by an e-beam through the thinned substrate, thereby locally transforming the bonding material into silicon oxide. Then a via opening is etched through the thinned substrate and an etch process selectively removes the oxide from an area delimited by the bonding material or vice versa. The filling of the via opening establishes an electrical connection between the bonded wafers, that is equivalent to a connection obtained by hybrid bonding, but that does not suffer from the disadvantages thereof.

## Claims

### Claim 1

A method of bonding a first semiconductor chip on a first substrate to a second semiconductor chip on a second substrate, comprising:
providing a bonding layer on at least one of the first substrate and the second substrate, the bonding layer being formed of a dielectric bonding material, wherein the dielectric material is Hydrogen Silsesquioxane (HSQ), or an equivalent thereof;
bonding the first substrate to the second substrate and performing a thermal annealing, so as to obtain a stack of the substrates with a bond layer between the first substrate and the second substrate, wherein the first substrate is thinned either before or after the bonding, and wherein the thermal annealing takes place at a temperature below a temperature at which the dielectric bonding material transforms into silicon oxide;
after bonding, scanning an electron beam across an area of the thinned first substrate, an energy of the electron beam being sufficient for the electron beam to reach the bond layer and to transform the scanned dielectric bonding material of the bond layer into a silicon oxide, to thereby obtain a volume of the bond layer that is transformed into a silicon oxide, wherein the volume is essentially a closed wall extending over a full thickness of the bond layer, and enclosing a volume of bonding material, thereby separating that volume of bonding material from the rest of the bond layer;
etching a via opening through the thinned first substrate until reaching an interior of the closed wall, and a dielectric liner is formed on sidewalls of the via opening;
through the via opening, removing the dielectric bonding material from the interior of the closed wall, selectively with respect to the silicon oxide, so as to create a cavity in the bond layer and expose a conductor in the second substrate; and
filling the cavity and the via opening with an electrically conductive material, to thereby form an electrical connection that connects the conductor in the second substrate to a conductor present in the first substrate and/or to a contact present on top of the stack.

### Claim 2 (depends on 1)

The method of claim 1, wherein after the removal of the dielectric bonding material from the interior of the closed wall, the stack is subjected to an additional thermal annealing at a temperature at or above the temperature at which the dielectric bonding material of the bond layer transforms into silicon oxide, to thereby transform the entire bond layer into silicon oxide.

### Claim 3 (depends on 1)

The method of claim 1, wherein a first bonding layer is provided on the first substrate and a second bonding layer is provided on the second substrate, and wherein the bond layer comprises a dielectric bonding layer obtained by bringing the first bonding layer and the second bonding layer into physical contact, followed by the thermal annealing.

### Claim 4

A method of bonding a first semiconductor chip on a first substrate to a second semiconductor chip on a second substrate, comprising:
providing a bonding layer on at least one of the first substrate and the second substrate, the bonding layer being formed of a dielectric material, wherein the dielectric material is Hydrogen Silsesquioxane (HSQ), or an equivalent thereof,
bonding the first substrate to the second substrate, and performing a thermal annealing, so as to obtain a stack of the first substrate and the second substrate with a bond layer between the first substrate and the second substrate, wherein the first substrate is thinned either before or after the bonding, and wherein the thermal annealing takes place at a temperature below a temperature at which the dielectric material transforms into silicon oxide,
after bonding, scanning an electron beam across an area of the thinned first substrate, an energy of the electron beam being sufficient for the electron beam to reach the bond layer and to transform the dielectric material of the bond layer into a silicon oxide, to thereby obtain a volume of the bond layer that is transformed into a silicon oxide, wherein the volume is a solid shape extending over a full thickness of the bond layer;
etching a via opening through the thinned first substrate until reaching the solid shape, and forming a dielectric liner on the sidewalls of the via opening;
removing, through the via opening, the silicon oxide of the solid shape selectively with respect to the dielectric material, so as to create a cavity in the bond layer and expose a conductor in the second substrate; and
filling the cavity and the via opening with an electrically conductive material, to thereby form an electrical connection that connects the conductor in the second substrate to a conductor in the first substrate and/or to a contact on top of the stack.

### Claim 5 (depends on 4)

The method of claim 4, wherein after the removal of the silicon oxide of the solid shape, the stack is subjected to an additional thermal annealing at a temperature at or above the temperature at which the dielectric material of the bond layer transforms into silicon oxide, to thereby transform the entire bond layer into silicon oxide.

### Claim 6 (depends on 4)

The method of claim 4, further comprising applying a continuous layer onto the first substrate prior to applying the bonding layer to the first substrate, wherein an additional liner is applied on top of the dielectric liner inside the via opening, and wherein a material of the continuous layer and of the additional liner is resistant to an etch process used to remove the silicon oxide of the solid shape.

### Claim 7 (depends on 6)

The method of claim 6, wherein the continuous layer and the additional liner are formed of silicon nitride.

### Claim 8

A stack of two or more semiconductor chips bonded by a bond layer consisting of Hydrogen Silsesquioxane (HSQ), or an equivalent thereof, wherein at least one electrically conductive pillar extends between two adjacent semiconductor chips of the stack, wherein the pillar is embedded in the bond layer formed between the two adjacent semiconductor chips, wherein individual ones of the semiconductor chips comprise an electrical conductor embedded in a respective dielectric layer, and wherein the stack further comprises a via connection extending from the top of a first semiconductor chip, through the dielectric layer of the first semiconductor chip, and partially overlapping the conductive pillar to connect the top of the first semiconductor chip to the electrical conductor of a second semiconductor chip.

### Claim 9 (depends on 8)

The stack of chips of claim 8, wherein the electrically conductive pillar forms an interior of a closed silicon oxide wall extending between the two adjacent semiconductor chips, the closed silicon oxide wall separating the bond layer from the electrically conductive pillar.

### Claim 10 (depends on 8)

The stack of chips of claim 8, wherein the electrically conductive pillar is in direct contact with the bond layer.