# US 11,114,331 B2 · Method for fabricating shallow trench isolation

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- Number: US 11,114,331 B2
- Document ID: US11114331B2
- Status: Granted
- Kind: B2
- Application number: 16/431,684
- Filed: 2019-06-04
- Published: 2020-11-05
- Granted: 2021-09-07
- Earliest claimed: 2019-05-03
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Hao-Hsuan Chang; Hung-Chun Lee; Shu-Ming Yeh; Ting-An Chien; Bin-Siang Tsai
- Web page: https://patentgrep.com/patent/US11114331B2

## CPC

- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10P 14/6524: {the substance being nitrogen}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/283: {by chemical means}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a pad layer adjacent to two sides of trench; forming a dielectric layer to fill the trench; and performing a dry etching process to remove the pad layer and part of the dielectric layer to form a shallow trench isolation (STI). Preferably, the dry etching process comprises a non-plasma etching process.

## Claims

### Claim 1

A method for fabricating semiconductor device, comprising:
forming a pad layer on a substrate, wherein the pad layer comprises:
a first pad layer on the substrate; and
a second pad layer on the first pad layer;
removing part of the pad layer and the substrate to form a trench;
forming a liner in the trench after removing part of the pad layer;
performing a nitridation process to divide the liner into a first portion and a second portion, wherein the second portion comprises a lateral extending portion covering an end portion of the first portion and flush with a top surface of the substrate;
after the nitridation process, forming a dielectric layer to fill the trench;
performing a planarizing process to remove the dielectric layer so that the top surfaces of the dielectric layer and the pad layer are coplanar;
removing the second pad layer;
after removing the second pad layer, performing a dry etching process to remove the first pad layer, part of the liner, and part of the dielectric layer at the same time to form a shallow trench isolation (STI), wherein the dry etching process comprises a non-plasma etching process, and after the dry etching process, a top surface of the liner comprises a curve, and a top surface of the dielectric layer comprises a planar surface that is flush with the top surface of the substrate; and
performing an anneal process to remove residues on a top surface of the substrate after removing the first pad layer and part of the dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first pad layer comprises silicon oxide and the second pad layer comprises silicon nitride.

### Claim 3 (depends on 1)

The method of claim 1, wherein the dielectric layer directly contacts the second portion of the liner and a sidewall of the first pad layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the second portion comprises nitrogen ions.

### Claim 5 (depends on 1)

The method of claim 1, further comprising performing an in-situ steam generation (ISSG) process to form the liner.

### Claim 6 (depends on 1)

The method of claim 1, wherein the dry etching process comprises hydrogen fluoride (HF) and ammonia gas (NH3).

### Claim 7 (depends on 1)

The method of claim 1, wherein the dielectric layer comprises silicon oxide.