# US 11,114,320 B2 · Processing system and method of forming a contact

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- Number: US 11,114,320 B2
- Document ID: US11114320B2
- Status: Granted
- Kind: B2
- Application number: 16/690,988
- Filed: 2019-11-21
- Published: 2020-06-25
- Granted: 2021-09-07
- Earliest claimed: 2018-12-21
- Assignees: Applied Materials, Inc.
- Applicants: Applied Materials, Inc.
- Inventors: Gaurav Thareja; Takashi Kuratomi; Avgerinos V. Gelatos; Xianmin Tang; Sanjay Natarajan; Keyvan Kashefizadeh; Zhebo Chen; Jianxin Lei; Shashank Sharma
- Web page: https://patentgrep.com/patent/US11114320B2

## CPC

- H10P 72/0468: {comprising a chamber adapted to a particular process}
- H10W 20/045: {for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/378: {Contact regions to the substrate regions}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10P 14/40: of conductive or resistive materials
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 72/0461: {characterised by the presence of two or more transfer chambers}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/048: {by using plasmas or gaseous environments, e.g. by nitriding}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/076: {in via holes or trenches}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Embodiments disclosed herein include a processing system and a method of forming a contact. The processing system includes a plurality of process chambers configured to deposit, etch, and/or anneal a source/drain region of a substrate. The method includes depositing a doped semiconductor layer over a source/drain region, forming an anchor layer in a trench, and depositing a conductor in the trench. The method of forming a contact results in reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.

## Claims

### Claim 1

A processing system comprising:
a system controller;
a first process chamber, wherein the system controller is configured to cause the first process chamber to deposit a doped semiconductor layer and a metal silicide layer on an exposed surface of a source/drain region of a substrate, wherein the source/drain region is exposed through a trench formed in a dielectric material formed over the source/drain region, and the source/drain region has a first dopant concentration and the doped semiconductor layer has a second dopant concentration higher than the first dopant concentration;
a second process chamber, wherein the system controller is configured cause the second process chamber to form an anchor layer over the metal silicide layer and sidewalls of the trench;
a third process chamber, wherein the system controller is configured to cause the third process chamber to fill the trench with a conductor; and
a fourth process chamber, wherein the system controller is configured to cause the fourth process chamber to heat the substrate to reflow the conductor within the trench.

### Claim 2 (depends on 1)

The processing system of claim 1, wherein the first process chamber is an epitaxial chamber, the second process chamber is a physical vapor deposition (PVD) chamber, the third process chamber is a chemical vapor deposition (CVD) chamber, and the fourth process chamber is an anneal chamber.

### Claim 3 (depends on 1)

The processing system of claim 1 further comprising:
a fifth process chamber, wherein the system controller is configured to cause the fifth process chamber to deposit a barrier layer over the anchor layer.

### Claim 4 (depends on 3)

The processing system of claim 3, wherein the system controller is configured to cause the fifth process chamber to deposit a cap layer over the metal silicide layer.

### Claim 5 (depends on 1)

The processing system of claim 1, further comprising:
a fifth process chamber, wherein the system controller is configured to cause the fifth process chamber to deposit a cap layer between the anchor layer and the metal silicide layer.

### Claim 6 (depends on 1)

The processing system of claim 1, further comprising:
a sixth process chamber, wherein the system controller is configured to cause the sixth process chamber to deposit an overburden layer over the conductor.

### Claim 7 (depends on 6)

The processing system of claim 6, wherein the sixth process chamber is a physical vapor deposition (PVD) chamber.

### Claim 8 (depends on 6)

The processing system of claim 6, wherein the anchor layer, the conductor, and the overburden layer comprise cobalt (Co).

### Claim 9

A processing system comprising:
a plurality of process chambers comprising:
a first process chamber configured to remove contaminant from an exposed surface of a source/drain region of a substrate, wherein the source/drain region is exposed through a trench formed in a dielectric material formed over the source/drain region;
a second process chamber configured to deposit sequentially a doped semiconductor layer and a metal silicide layer over the source/drain region, wherein the source/drain region has a first dopant concentration and the doped semiconductor layer has a second dopant concentration higher than the first dopant concentration;
a third process chamber configured to deposit a barrier layer on the metal silicide layer and sidewalls of the trench;
a fourth process chamber configured to deposit an anchor layer over the barrier layer;
a fifth process chamber configured to fill the trench with a conductor;
a sixth process chamber configured to deposit an overburden layer over the conductor; and
a seventh process chamber configured to heat the substrate to reflow the conductor within the trench.

### Claim 10 (depends on 9)

The processing system of claim 9, wherein the second process chamber is an epitaxial chamber, the third process chamber is an atomic layer deposition (ALD) chamber, the fourth process chamber is a physical vapor deposition (PVD) chamber, the fifth process chamber is a chemical vapor deposition (CVD) chamber, the sixth process chamber is a PVD chamber, and the seventh process chamber is an anneal chamber.

### Claim 11 (depends on 9)

The processing system of claim 9 further comprising:
a first transfer chamber coupled to one or more of the plurality of process chambers, the first transfer chamber configured to transfer the substrate to and receive the substrate from the one or more of the plurality of process chambers coupled to the first transfer chamber.

### Claim 12 (depends on 11)

The processing system of claim 11, further comprising:
a pass-through chamber coupled to the first transfer chamber; and
a second transfer chamber coupled to the pass-through chamber.

### Claim 13 (depends on 9)

The processing system of claim 9, wherein the anchor layer, the conductor, and the overburden layer comprise cobalt (Co).

### Claim 14 (depends on 9)

The processing system of claim 9, wherein the third process chamber is configured to form a cap layer between the barrier layer and the metal silicide layer.

### Claim 15 (depends on 14)

The processing system of claim 14, wherein the barrier layer and the cap layer comprise nitrogen (N).

### Claim 16

A method of forming a contact, comprising: depositing a doped semiconductor layer over an exposed surface of a source/drain region of a substrate, wherein the source/drain region is exposed through a trench formed in a dielectric material formed over the source/drain region; depositing a metal silicide layer over the doped semiconductor layer in a first process chamber;
transferring the substrate to a second chamber to form an anchor layer over the metal silicide layer and sidewalls of the trench; transferring the substrate to a third chamber to fill the trench with a conductor; and
transferring the substrate to a second chamber to heat the substrate such that the conductor reflows within the trench; wherein the source/drain region has a first dopant concentration, and the doped semiconductor layer has a second dopant concentration higher than the first dopant concentration.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
depositing a barrier layer over the metal silicide layer; and
forming an overburden layer over the conductor.

### Claim 18 (depends on 17)

The method of claim 17, wherein
the anchor layer and the conductor comprise cobalt (Co), and
the barrier layer comprises nitrogen (N).

### Claim 19 (depends on 16)

The method of claim 16, further comprising planarizing the substrate, the planarizing the substrate comprising a chemical mechanical polishing (CMP) process.