Chip packaging method and package structure

A chip package structure, comprising:

• at least one die;
• a protective layer provided on a die active surface of the at least one die, the protective layer comprises a composite protective layer with filler particles, wherein a plurality of conductive filled vias are provided in the protective layer, and at least one of the conductive filled vias is electrically connected with die pads provided on the die active surface, wherein side protective layer surfaces are substantially aligned with side die surfaces;
• an encapsulation layer, the encapsulation layer encapsulating the at least one die;
• a conductive layer, at least partially provided on a surface of the protective layer, wherein at least a part of the conductive layer is electrically connected with the conductive filled vias;
• a dielectric layer, provided on the conductive layer;
• and
• wherein the protective layer comprises
• Young's Modulus and a protective layer thickness which are configured to
• provide buffering and support for the conductive layer to prevent die breakage,
• and prevent burring and chipping from a singulation process to separate a wafer processed with dies into individual dies, and
• a coefficient of thermal expansion configured to prevent interface stress and interface fatigue between the die and the protective layer.